Journal of VLSI Design Tools and Technology
Electrical Engineering ISSN 2249-474X 3 issues a year Hybrid open access
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About the journal
Journal metrics
Counted from this archive, not supplied by anyone.
- 42Articles published
- 9Published in 2026
- 118Authors
- 3Open access
Journal information
- Title
- Journal of VLSI Design Tools and Technology
- Issues per year
- 3 issues
- ISSN
- 2249-474X
- Publisher
- STM Journals
- DOI
- 10.37591/JoVDTT
- Starting year
- 2024
- Subject
- Electrical Engineering
- Publication format
- Hybrid open access
- Language
- English
- Type
- Peer-reviewed journal (refereed)
Indexed in
Editorial board
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Editor-in-Chief
Department of Electronics and Communication Engineering, Indian Institute of Technology, Roorkee, India
Latest articles
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A Physics-Informed Graph Neural Network Framework for Real- Time Thermal-Aware Fault Prediction and Adaptive Power Optimization in Heterogeneous System-on-Chip Architectures
Abstract: Heterogeneous System-on-Chip (SoC) architectures are increasingly adopted in edge computing, artificial intelligence, autonomous systems, and high-performance embedded platforms due to their superior computational efficiency and flexibility. However, increasing integration density and workload diversity introduce severe thermal hotspots, accelerated device degradation, and unexpected hardware faults that adversely affect system reliability and energy efficiency. This study proposes a Physics-Informed Graph Neural Network (PI-GNN) framework for real-time thermal- aware fault prediction and adaptive …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 Read article
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Performance and Analysis of 6T, 8T & 10T SRAM Cell in 28nm Technology
Abstract: Technology scaling into deep sub-micron regimes has significantly increased the design challenges of Static Random Access Memory (SRAM), particularly at the 28 nm technology node. As transistor dimensions shrink, SRAM cells become more vulnerable to stability degradation, leakage current, process variations, and reduced noise margins, which adversely affect overall memory performance and reliability. The conventional 6T SRAM cell remains widely used due to its compact structure and high storage density; …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 Read article
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Thermally Adaptive Bio-Inspired VLSI Interconnect Model for Next-Generation Embedded Systems
Abstract: The increasing complexity of next-generation embedded systems has intensified the challenges associated with power dissipation, thermal instability, signal integrity, and interconnect reliability in Very Large- Scale Integration (VLSI) architectures. This research proposes a thermally adaptive bio-inspired VLSI interconnect model designed to enhance communication efficiency and thermal resilience in advanced embedded platforms. The proposed model integrates bio-inspired adaptive routing principles with dynamic thermal-aware interconnect management to optimize data transmission under varying …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 2, 2026 Read article
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Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits
Abstract: This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption. Moreover, the CMOS inverter design will be created using the Cadence Virtuoso design environment, along with a post-layout analysis of the design. Performance evaluation of the designed circuit will be carried out through the execution of a transient analysis …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 40–57 Read article
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Design & Implementation of 16-BIT MAC Unit Using Vedic Mathematics
Abstract: Multiply and Accumulate (MAC) units are essential parts of digital systems, particularly in embedded systems, digital signal processing (DSP), and image processing. The performance of these systems is significantly impacted by how well the multiplication process works. The design and construction of a fast 16-bit MAC unit utilizing Vedic mathematics are presented in this study.The proposed design utilizes the Urdhva Tiryagbhyam sutra to perform multiplication in a parallel manner, reducing …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 52–58 Read article
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A well-planned strategy for a career path in VLSI design
Abstract: Very Large Scale Integration (VLSI) design is still one of the most active and important areas of the semiconductor industry. It is behind new developments in AI, 5G, automotive electronics, and high-performance computing. As companies like Intel, TSMC, and NVIDIA work to improve advanced-node technology, the need for qualified VLSI engineers is growing. However, people who want to work in this industry typically don't know what technical skills, tools, and …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 28–39 Read article
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A Review on Two-Wheeled Self-Balancing Robot Using Spartan-3E FPGA for Sensor Fusion and Real-Time Motor Control
Abstract: Two-wheeled self-balancing robots (TWSBR) are a popular application of embedded control and robotics because they operate on the inverted pendulum concept, which is naturally unstable. The main objective of such robots is to continuously maintain balance by estimating the tilt angle and applying corrective motor action in real time. In most practical systems, low-cost inertial sensors such as accelerometers and gyroscopes are used for tilt measurement. However, accelerometer readings are …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 17–27 Read article
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A study on CMOS Operational Amplifier in Sensor Development
Abstract: CMOS operational amplifiers (op-amps) have emerged as pivotal components in modern sensor development, enabling the amplification and conditioning of weak signals with high precision and efficiency. Their inherent advantages low power consumption, compact size, and seamless integration with digital circuits make them ideal for advancing miniaturized, battery-powered sensor systems in fields ranging from biomedical devices to IoT networks. By delivering precision, power efficiency, and integration, CMOS op-amps are not just …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 01–07 Read article
Ahead of print
Accepted and online before they are assigned to an issue.
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Design and Simulation of Forging Die Towards Improving Life of Closed Die
Abstract: Forging is the metal forming process which is used for forming complex shaped component with geometrical accuracy. More than fifty percent of the forgings are processed through this way. Forged components required in many engineering sectors, most of them in the automotive sector. The majority of the safety critical component and load bearing structural components are process through it. By using forging process production of complex component is faster with …
Published in Journal of VLSI Design Tools and Technology Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article