Journal of VLSI Design Tools and Technology
Volume 5, Issue 1 (2015)
Published
Table of contents
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Designing of GaAs Based Resonant Tunneling Diode and Nano Scale Applications with Considering NEGF
Abstract: Present situation of eletronic area in the world required small devices as well as low power dissipation and ultra high speed application. At this moment the presence of resonant tunneling diode can over come this type of problem and take a big role in nanoscale digital and analog applications.In this researh article is to demonestrated effect of asymmetric barrier with respect to symmetric barrier and digital inverter and THz analog …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 1–18 Read article
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Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology
Abstract: In this paper power consumption of Gated diode DRAM (Dynamic Random Access Memory) cells are carried out. This analysis is carried out on 32 nm scale. The DRAM cell used here are 3T1D and 2T1D DRAM cell. Static, total average and transient power for both types of cells are simulated in order to have a comparison of their performance on the same technology. A comparative study of different types of …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 19–23 Read article
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Hybrid CMOS-SET Inverter Design for Improved Performance using Tied Body-backgate Technique
Abstract: Single-electron transistors (SETs) are an attractive candidate for future functional elements in LSIs, because of their low-power consumption and small size. Integration of current CMOS technology with the emerging SET devices is an effective approach for improving density of integration in VLSI chips and ensuring ultra low power dissipation along with the advantages of CMOS technology like high gain, current drive, speed and matured fabrication technology. This paper investigates hybrid …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 24–29 Read article
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Optimized AES Implementation on Leon3
Abstract: This paper presents implementation of AES (Advanced Encryption Standard) on LEON3 which is a soft-core processor. We have used the AMBA (Advanced Microcontroller Bus Architecture) bus for interfacing our AES IP (Intellectual Property) core with Leon3 processor. AMBA bus is an in built open source bus which comes along with Leon3 processor. We have mainly analyzed parameters such as throughput, slice utilization and compared our model based with previous work. …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 30–33 Read article
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Real Time FPGA-based Embedded Architecture of Audio Compression and Decompression Core for Multimedia System
Abstract: A multimedia system links images and audio to distribute and transmit information to users. These images and audio data have to be compressed for raising capacity of storing and processing tasks in real time without losing the required information. This paper introduces an audio processing unit by using the FPGA hardware board. This is a complete Embedded system where the audio compression and decompression core is firstly described as a …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 34–44 Read article
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Which is the Best 10T Static CMOS Full Adder for Ultralow-Power Applications?
Abstract: This paper presents the analysis of various 10-transistor CMOS 1-bit full adder circuits in terms of their output levels and finds out the suitable adder cell at 200 mV in subthreshold region at 16-nm technology node for ultra-low power applications. This paper also provides worst case output levels (sum and carry) of all the analyzed adder cells (which are presented in the paper) for various input combinations.Keywords: CMOS, carry, 2:1 …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 45–50 Read article
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Characterization of High Speed Phase Frequency Detector Circuit
Abstract: In this paper the performance of high speed phase frequency detector (PFD) is analysed. A high-speed PFD reduces the power consumption of traditional PFD to 0.423 nW at 1 GHz clock frequency and dead zone to 2 ps. It is suitable for low power applications. A PFD uses only 18 transistors. This PFD operates up to 1 GHz at 1.2 V supply voltage. The proposed architecture of the PFD has …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 51–58 Read article