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Journal of VLSI Design Tools and Technology

Characterization of High Speed Phase Frequency Detector Circuit

  1. Nilesh D. Patel
  2. Amisha P. Naik

Abstract

In this paper the performance of high speed phase frequency detector (PFD) is analysed. A high-speed PFD reduces the power consumption of traditional PFD to 0.423 nW at 1 GHz clock frequency and dead zone to 2 ps. It is suitable for low power applications. A PFD uses only 18 transistors. This PFD operates up to 1 GHz at 1.2 V supply voltage. The proposed architecture of the PFD has been implemented using 0.35μm CMOS technology and 90 nm CMOS technology.Keywords: low power PFD, phase frequency detector, phase-locked loop, PLLCite this Article:Nilesh D. Patel, Amisha P. Naik, Characterization of High Speed Phase Frequency Detector Circuit, Journal of VLSI Design Tools and Technology (JoVDTT).2015; 5(1): 51–58p.
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