Journal of VLSI Design Tools and Technology
Volume 6, Issue 3 (2016)
Published
Table of contents
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Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy
Abstract: The development of digital circuits, digital signal processors and other data processing integrated circuits, comparators are challenged by large area consumption. Comparator is most basic and fundamental component that performs comparison operation. This paper proposes a new approach to design an area efficient two bit magnitude comparator. Comparison is done on the grounds of area and power consumed between circuit designed by novel strategy and preexisting CMOS technique. The novel …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 1–6 Read article
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Design of FPGA Based ALU Using Reversible Logic Gates
Abstract: Reversible or information misfortune less circuits has applications in computerized signal handling, correspondence, PC design and nanotechnology. Reversible technique is utilized to minimize heat that happens in traditional circuits by keeping the loss of data. This paper proposes a reversible configuration of an ALU. This ALU comprises of eight operations, five are of arithmetic category and three are from logical category operations. An arithmetic operations incorporate add, sub, increase by …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 15–21 Read article
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Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers
Abstract: More sophisticated designs of communicating devices are required with tremendous scaling in MOS. Mixers play a vital role in all radio transmitters and receivers. To improve the sensitivity of the receivers, the low noise amplifiers are designed with very high gain. Higher gain of amplifier saturates the preceding sections and forces them to operate in the nonlinear region. MOS based Single Balanced and Double Balanced mixers are the most common …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 22–27 Read article
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Development of System for Speech Enhancement using Combinational Adaptive LMS on Reconfigurable Platform
Abstract: Low cost and robustness makes the least mean square (LMS) algorithm most popular. Improved adaptive filter performance can be obtained by combinational approach. In this paper, for speech enhancement, we used one of such approaches known as ‘filter combination’. As our simulation results show, Fixed-Sign LMS algorithm overcome other algorithms in terms of SNR and mean square error. Keywords: Adaptive filter, speech enhancement, windows, convex combination
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 28–34 Read article
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Design of High-Speed and Low-Power Carry Skip Adder
Abstract: In this brief, we present a high speed and lower power consumption carry skip adder (CSKA) architecture compared with the conventional one. The increment of speed is attained by implementing concatenation and incrementation strategy to improve the efficiency of the conventional CSKA (Conv-CSKA) architecture. Instead of make use of multiplexer logic, the proposed architecture makes use of AND-OR-Invert (AOI) and OR-AND-Invert (OAI) combination gates for the carry skip logic. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 35–44 Read article
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A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique
Abstract: In the present arena of technology scaling, the power consumption in the deep submicron technology plays a pivotal role as the transistor counts increases dramatically. Therefore, the need of the hour is to focus on power dissipation. The rate of occurrences of errors in the present VLSI scenarios has become higher and inevitable, and is increasing along with technology scaling. Eradicating all the errors is a cumbersome task; still a …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 45–55 Read article
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Survey of System-on-Chip Modular Test Approach
Abstract: The advancement in semiconductor technology over the past few decades has enabled the industry to develop new design and reuse methodologies referred as System-on-chip (SoC) design. These typically integrate heterogeneous mix of various complex analog and digital cores, with all their necessary electronic circuitry. The recent advancements have led to the use of the 3D structures (3D-SOCs) that brought along the benefits of higher performance, minimum average interconnect length, reduced …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 56–70 Read article
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Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier
Abstract: Multiplication, a very important arithmetic operation, is finding a great use these days in various applications (especially DSP, multimedia and image processing). Due to advances in technology and increasing needs for high-speed calculations, it has become really necessary and important to design a fast efficient multiplier. A productive method to speed up the multiplication is reduction in the Partial Product (PP) array. In this paper, the design of 8, 16 …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 7–14 Read article
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Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications
Abstract: In this paper, two designs of flash analog to digital converters (ADCs) based on threshold inverter quantization (TIQ) technique are presented. The parallel threshold inverter quantization (PTIQ) flash ADC exploits the advantage of reduction in capacitance and power consumption if the transistors are placed in parallel. Another design called low voltage tunable body bias (LVTBB) PTIQ ADC operates at near threshold voltage level to minimize the power consumption. The PTIQ …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 71–87 Read article
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VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter
Abstract: As the technology progresses, a large number of devices can be incorporated into a single chip. So, the communication between these devices becomes critical. The network-on-chip (NoC) is a technology used for such communication and overcomes the constraints of traditional bus-based system-on-chip (SoC). Router is the backbone of NoC and determines the performance to a great extent. This paper focuses on the implementation of five port virtual channel router which …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 88–93 Read article