Journal of VLSI Design Tools and Technology
Volume 1, Issue 1-2-3 (2011)
Published
Table of contents
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An Explicit Approach to Compare Crosstalk Noise and Delay in VLSI RLC Interconnect Modeled with Skin Effect with Step and Ramp Input
Abstract: As the technology is acquiring frequency of the Giga-hertz range noise and delay calculations andavoidance of such factors in VLSI interconnects have become dominant to be considered. This paperrepresents a comparison between the crosstalk noise voltage level measured when the RLC on-chipinterconnect was modeled when the skin effect was considered under step input and the crosstalk voltagemeasured when the RLC line was modeled with skin effect under ramp input. In …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 1–8 Read article
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Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETs in Nanoregime
Abstract: In this paper, performance of the VLSI circuits designed with strained silicon MOSFETs is analysed andcompared with bulk MOSFET. Emphasis is being given on the evaluation of speed, power and noisecharacteristics. An inverter circuit designed with single channel and dual channel biaxial strained MOSFETsof 40 nm channel length and 0.3 germanium mole-fraction is being taken to evaluate the performance throughsimulation. The device design and circuit simulation is done in Sentaurus …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 15–20 Read article
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Automatic Switch cum Fuse IC for Low Voltage, Low Power, High Performance Current Conveyors
Abstract: The paper focuses on the analysis of switch cum fuse IC in signal processing. In signal processing it is proposedto prevent the damage of main IC from the external electrical fluctuations which are common in -these days. Theproposed FUSE IC is also able to act as fuse for many times for main IC so that it can prevent the damage. It’slike the work of MCB but a step ahead that …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 21–25 Read article
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Gain Controlled Sinusoidal Oscillator Using Current Controlled Current Conveyors
Abstract: A gain-controlled sinusoidal oscillator circuit based on current-controlled current conveyors (CCCII) is introduced. The circuit contains three CCCIIs and two grounded capacitors and no resistor. The amplitude of the output current can be controlled electronically. Hence, the proposed topology is suitable for IC implementation. The CCCII has been implemented using 0.35 μm CMOS technology and the PSPICE simulation results are given.
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 26–30 Read article
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Modelling of Skin Effect in On-Chip VLSI RLC Global Interconnect
Abstract: This paper addresses one of the aspects of the high frequency effects, namely the skin effect. The basicproblem with skin effect is that it attenuates the high frequency components of a signal more than that ofthe low frequency components. Due to the increase in operating frequency and die sizes, RC models arebecoming insufficient for analysis of global VLSI interconnects. Accurate noise modelling for RLC lines isthus critical for timing and …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 31–44 Read article
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Power Estimation for VLSI Circuits Using Neural Networks
Abstract: Neural network based VLSI power estimation is done which estimates power in VLSI circuits from its input/output and gate information, without simulation and analysis of its detail structure and the interconnections.Artificial neural network is created which helps in estimation of power. Power estimation results from the [2] [3]are used as the training vector for the network .The network is trained using Back-propagation algorithm. Asimple recurrent network is also introduced called …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 45–56 Read article
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Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network at 0.18 µm Technology
Abstract: In this model, the time domain waveform is evaluated for calculation of delay time, peak time, settling time, damping ratio and natural frequency for a second order RLCG interconnect network. It can also be used for multiple interconnect systems but for higher order systems it is ignored due to accurate analysis. The model is applied to a single resistance-inductance-capacitance-conductance model which can also be extended to multi-interconnect systems to analyze …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 57–67 Read article
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Analysis of Resource Utilization for a Floating-Point Complex Multiplication in FPGA
Abstract: Complex multiplication is an important operation frequently used in the digital signal processing. This paper shows the resource utilization for a complex multiplication on Spartan3E by using a 9 bit floating point numbers. The proposed method clearly shows that resource utilization for complex multiplication is less than the IP cores proposed by the Xilinx Company. More over this paper shows how the significant and the exponent of the floating point …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 9–14 Read article