Journal of VLSI Design Tools and Technology
Volume 10, Issue 3 (2020)
Published
Table of contents
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The Study on Energy-Efficient Context-Aware Architecture for Wired or Wireless Communication System
Abstract: The ever-increasing technical developments in the engineering of embedded systems, along with The proliferation of small sensor design and implementation has allowed mobile devices (e.g. Smartphones) understand everyday human acts, events and experiences. Consequently, inferring a wide spectrum of mobile application user-based behaviours from a very diverse background gathered from a collection of sensory measurements has attracted a great deal of attention in the field of ubiquitous sensing science. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 1–8 Read article
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Wire Network Survivability for Upgraded Consistency in Smart Power Grids
Abstract: Power transmission system infrastructures transmit energy over a long distance and are essential to the operation of urban society. These configurations progressively reflect highly coupled cyber-physical structures where automated telecommunications networks are used to transmit status and control details to power transmission grid elements, i.e. smart grids. However, due to the high degree of interdependence between the contact and power grid layers, malfunction incidents may contribute to more loss of …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 16–21 Read article
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Design, Implementation and Comparative Analysis of Different 8-Bit Multipliers Based on Power, Delay and Hardware Utilization
Abstract: Multipliers play important role in the digital VLSI design. Computational Speed, power consumption, and area are the major parameters on which the performance of the device depends. In digital design, there are different multiplication methods or algorithms. Each algorithm is having its own advantage and disadvantage. In this paper, implementation of five different types of 8-bit multipliers namely Array multiplier, Booth multiplier, Truncated multiplier, Pipelined multiplier, and Vedic multiplier has …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 22–34 Read article
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Hierarchical Methodology Approach to SOC Design: A Comprehensive Look
Abstract: The design scale of a chip has increased many folds in the last few years and shows a continuous exponential trend. This is made possible by the reduction in transistor size and an evolving process technology. As a result, it is possible to move to SoC technology (System on Chip-A single die consisting of multiple subsystems) rather than a traditional ASIC. This has obviously resulted in an increase in the …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 35–42 Read article
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A Review on Mechanization of Process Planning for Automated Fiber Placement
Abstract: Process planning is a crucial phase of the Automatic Fiber Placement (AFP) workflow. It creates valuable and effective system processes centered on working material, composite architecture and manufacturing tools. The existing state of process planning needs a large degree of involvement from the process manager and may benefit significantly from improved automation. A collection of main stages and roles is then drawn up to define the most complex and time-consuming …
Published in Journal of VLSI Design Tools and Technology · Vol. 10, Issue 3, 2020 · pp. 9–15 Read article