Journal of VLSI Design Tools and Technology
Volume 5, Issue 3 (2015)
Published
Table of contents
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A Review on Charge Pump Circuits for PLL Applications
Abstract: This paper presents a review on various architectures of charge pumps (CP) for high speed Phase-locked loop (PLL) applications. The different nonlinear marvels that influence the execution of PLL in view of the CPs circuit are examined. The various high performance CP circuits with reference voltage source, reference current source are analyzed that reduces the problems associated with the traditional charge pump circuit that consists leakage current, clock feed-through, charge …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 1–11 Read article
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All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey
Abstract: An all-digital phase locked loop (ADPLL) plays a great role in decreasing the development time of an application-specified integrated circuit (ASIC) products and helps to meet the time-to market requirement of product, because an ADPLL can be used as an IP core, so it is easily reusable in any design. Now a days ADPLL is being widely used in various fields such as control systems and digital communication systems. This …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 12–17 Read article
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CMOS Gm-C IF Filter using SCA for Dual Band Receiver
Abstract: This paper deals with design of folded cascode OTA-C filter, which works for frequencies for RF application, based on transistor sizing methodology and simulation results are performed using SPICE software and BSIM3V3 model for CMOS 0.18 μm process, show that the designed folded cascode OTA has a 52 dB DC gain and provides a unit gain bandwidth of around 400 MHz. Design of CMOS Gm-C 2nd order Biquad filter implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 18–36 Read article
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Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology
Abstract: Low noise amplifier (LNA) is terribly important block in designing broadband receivers for wireless broadband communications. Being the primary active element in receiver chain it creates larger demand for LNAs that are smaller, consume less power, and provide sufficient gain, low noise and high compact design. The projected LNA is extremely integrated with low noise figure having wide calibration range with improved RF power handling system and acquires less space …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 37–44 Read article
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Memristor Modelling for Common Source Amplifier Using 180 nm Technology
Abstract: The objective of this research paper is on memristor modeling for common source amplifier circuit using cadence virtuoso tool at gpdk 180 nm technology. A memristor is the fourth element count after resistor, inductor and capacitor in fundamental electrical circuits assumption is proposed by Leon Chua, its characteristics is based on already occurred principles of voltages (V), current (I), flux (ᵩ) and charge (q). Ohm’s law states relation voltage to …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 45–54 Read article
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Design and Implementation of an Efficient Ternary Control Unit
Abstract: Multi-valued logic (MVL) is emerging as a thrust area of research due to several advantages offered by them over the conventional binary logic. Ternary logic is a promising alternative to the binary logic design technique thereby attracting a wide community of researchers to contribute in the design of ternary processor. The control unit is effectively the nerve center of a processor that plays a vital role in generating the appropriate …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 3, 2015 · pp. 55–70 Read article