Journal of VLSI Design Tools and Technology
Volume 8, Issue 3 (2018)
Published
Table of contents
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Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter
Abstract: Circular retiming improves performance and power consumption of the Least Mean Square (LMS) adaptive filter. It is implemented for weight updated block and error computational block to minimize the adaptive filter error without violating the functional equivalence output. Here, filter multiplication block is updated in a circular convolution format and is retimed to reduce the dynamic power consumption. Additional retime flip-flops shows better performance result compared with the existing state-of-the-art …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 1–9 Read article
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An Area Delay Optimized Carry-Select Adder
Abstract: In arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 10–14 Read article
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Design, Verification and Circuit Level Implementation of a Ballistic MOSFET
Abstract: A drain current expression is obtained for a nanoscale ballistic MOSFET within the framework of Landauer-Buttiker formalism considering intrinsic silicon channel at low temperature. The model drain current is compared with the numerical simulations of near ballistic nanoMOSFET structure. There is a reasonable agreement between the model and the numerical simulation results. This demonstrates the remarkably low value of the subthreshold slope of ballistic nanoMOSFET. Further, the design structure is …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 15–22 Read article
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Performance Analysis of CMOS and FinFET Based SRAM
Abstract: As CMOS devices are scaled to nanometer regime, the consequences such as short channel effects and variations in the process parameters are increased which affects the reliability and performance of the circuit. In order to over these issues, FinFET can be used as a suitable replacement for CMOS as it is a promising and better technology without sacrificing the reliability and performance of the applications and the circuit design. In …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 23–27 Read article
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Design and Analysis of MAC Unit Using Single Precision Floating Point Vedic Multiplier
Abstract: Multiplication and accumulation are the basic operations which are important in several microprocessors and digital signal processing (DSP) applications to execute dedicated algorithms. Developing high speed MAC is essential for real time DSP application. The MAC unit determines the speed of the overall system and it lies in the critical path. As the demand for high speed design is continuously increasing, the studies related to the field of multipliers and …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 28–35 Read article
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A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network
Abstract: Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately, solve the communication problem, and to obtain high-performance integrated circuits. In this study, the International Technology Roadmap for Semiconductors (ITRS) is used as a reference to fulfill the requirements of silicon-based ICs must satisfy to successfully perform copper electrical interconnects (IEs). Keywords: Integrated optoelectronic circuits, optoelectronics, optical interconnects (ICs), silicon photonicsCite this ArticleAbhishek Sharma, Sudhir Kumar …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 36–44 Read article
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A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions
Abstract: Double-Gate tunnel FET devices, which uses high-κ gate dielectric, are explored using realistic design parameters, showing an ON-current as high as 0.23 mA, a gate voltage of 1.8 V, an OFF-current of not more than 1 fA (neglecting gate leakage), an improved ordinary subthreshold swing of 57 mV/dec, and a lower point slope of 11 mV/dec. A dual material control gate tunnel field effect transistor for an asymmetric doping at …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 45–53 Read article