Journal of VLSI Design Tools and Technology
Volume 9, Issue 1 (2019)
Published
Table of contents
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Implementation and Analysis of 32-bit pipelined RISC Processor Architecture
Abstract: Pipelining is an implementation technique, in which parallel operations are performed for several instructions simultaneously, to save time, enhance speed and for better utilization of hardware units. In this paper, 32-bit, 5-stage RISC processor is used to tag the pipeline stages to obtain the optimized results. The architecture of the processor containing several elements reduces the debugs and upholds the high performance through critical functions. When compared to our closest …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 1–14 Read article
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Design of Active Filter using CMOS based IInd Generation Current Conveyor in Current Mode
Abstract: Traditional design techniques used in VLSI are in voltage mode, but these have drawbacks like low bandwidth, non-linearity and less gain. Current conveyors act similar to operational amplifiers but are advantageous over older VLSI design techniques because of high bandwidth-gain product, reduced power consumption etc. This paper consists of two parts: circuit diagram of current conveyor (which is a three terminal analog device) is discussed first and its working is …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 15–21 Read article
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Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications
Abstract: Clock distribution network consumes significant amount of power due to its high switching activity. The high power consumption issue can be satisfactorily addressed by the sub-threshold operation of device, however at the cost of degraded performance and magnified variability. This paper investigates the suitability of conventional clock distribution network for sub-threshold regime and proposes a novel strategy of having an optimized uniform H-tree with a pair of buffer only at …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 22–37 Read article
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Implementation of Different Low Power Techniques on CMOS Inverter and NAND Circuits
Abstract: The growth in technology has increased the usage of additional components on a single chip. This increased number of components on a single chip increases the significant amount of power dissipation and this causes the major challenge for the today’s circuit designers. There are several techniques in VLSI field which help to reduce power dissipations. This paper has analytical analysis of different low power techniques on CMOS inverter and NAND …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 38–43 Read article
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Near Field Wireless Powering of Implantable Devices
Abstract: A new WPT system for biomedical applications has been investigated in this paper. First, an implantable receiving antenna with enhanced gain is studied. Then, a transmitting antenna array which can maximize the PTE of the WPT system is designed together with the receiving antenna and head model. Under the transmission distance of 150 mm, the PTE of the designed WPT system reaches a maximum value of 0.28% at the center …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 44–50 Read article
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Reusable FM0/Manchester Encoding Using QCA
Abstract: Dedicated short range communication (DSRC) is an important technique which is used for transmission of high speed data in communication based safety applications. For signal reliability and dc balance, it uses either Manchester or FM0 coding technique. Code word structure for both FM0 and Manchester are different, which makes limitation on the hardware potential of DSRC system So, SOLS technique is used to conquer this limitation which combines the hardware …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 51–59 Read article