Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications

Rupali Ashok Walunj; Sachin Dattatraya Pable; Gajanan Kashiram Kharate

doi:10.37591/jovdtt.v9i1.1402

Abstract

Clock distribution network consumes significant amount of power due to its high switching activity. The high power consumption issue can be satisfactorily addressed by the sub-threshold operation of device, however at the cost of degraded performance and magnified variability. This paper investigates the suitability of conventional clock distribution network for sub-threshold regime and proposes a novel strategy of having an optimized uniform H-tree with a pair of buffer only at sink nodes in CDN. The performance of various configurations in which the pair of buffer can be connected is investigated. Finally, the optimized uniform H-tree with CMOS buffer connected to sink node and followed by dynamic threshold MOS (DTMOS) buffer is proposed. The simulation results indicate that a tenfold time’s improvement in slew is exhibited by proposed clock distribution network with added advantage of reduced power consumption as compared to conventional clock distribution network. Along with improvement in slew, its control is utmost important to ensure reliable operation of synchronous system. Therefore variability analysis is also accentuated in this paper. The results exhibit that the proposed clock distribution network is robust compared to conventional clock distribution network. Keywords: Sub-threshold, Ultra Low Power (ULP), Clock Distribution Network (CDN), Dynamic Threshold MOS (DTMOS), slewCite this ArticleR.A. Walunj, S.D. Pable, G.K. Kharate. Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications. Journal of VLSI Design Tools & Technology. 2019; 9(1): 22–37p.