Journal of VLSI Design Tools and Technology
Volume 4, Issue 2 (2014)
Published
Table of contents
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A Cuckoo Search based Approach for Solving Standard Cell Placement Problem
Abstract: The standard cell placement (SCP) is an NP complete problem in VLSI layout which focuses on placing the cells at appropriate locations so as to minimize the resultant wirelength. The standard cell placement is one of the significant phases in VLSI circuit design. Many heuristic approaches have been developed in literature to solve this problem. The paper presents an efficient nature-inspired meta-heuristic algorithm for solving the standard cell placement problem …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 1–7 Read article
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A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit
Abstract: A size and power efficient current-mode decimal adder is proposed in this paper. The proposed adder does not use binary coded decimal (BCD) number system for processing the decimal data like other decimal adders. Instead, it processes the decimal data as the actual decimal inputs. The proposed adder can be used as a decimal half adder as well as a decimal full adder. The adder is based on simple decimal …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 18–23 Read article
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A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits
Abstract: Today the integrated circuit’s functionalities are increasing day by day with increase in the number of transistors in it. However, the scaling of the transistors, top increase its number, for the same area of an IC reduces its sub-threshold voltage with its increase in the leakage power consumption. Scaling at different scales (45, 60, 90 nm, etc.) leads to major losses, both at static and dynamic phases of the circuits. …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 24–31 Read article
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Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers
Abstract: VLSI design technology suffers from three major issues such as area, speed and power. Among these issues, power is a serious concern that is yet to be considered. So, in this paper, power is concerned more as compared to area and speed. GDI (gate diffusion input) is one of the common techniques used in VLSI design systems to reduce power consumption. Due to its high performance and less area overhead, …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 32–36 Read article
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A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture
Abstract: A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 37–46 Read article
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Design of High-Speed TIQ Comparator for Flash-Type ADC for (WPMOS/LPMOS) > 1
Abstract: Comparator is the circuit that compares an analog signal with the reference signal and produces the binary output based on comparison. A Comparator is the main block in the ADC design as it directly affects the conversion rate of an ADC. Depending on the type and architecture of the comparator, the comparator can have significant impact on the performance of the target application. The speed and resolution of an ADC …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 47–52 Read article
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Comparative Analysis of Low-Power Adiabatic Techniques
Abstract: In today’s modern era, new revolutionary designs are replacing old traditional bulky designs. Due to advancements in technology, low-power designs are in demand. Advantages of adiabatic technique can be used for overcoming disadvantages of typical CMOS such as dissipated energy loss. Adiabatic techniques are extremely reliant on parameter changes. In this paper, the merits of adiabatic techniques are depicted on the basis of parameter variations. By the use of SPICE …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 53–58 Read article
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Performance Estimation of VLSI Design
Abstract: This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 59–66 Read article
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Triangular Waveform Generation using Mixed Signal Modeling
Abstract: The development of modeling languages such as Verilog-HDL and Verilog-AMS allows the behavior of analogue and mixed signal circuits to be described with a more lucid way as compared to the conventional circuit-level simulators. Mixed-signal simulators are thus providing a new platform for more efficient modeling of mixed signal that contains both the analogue and discrete features which was not previously possible. The non-linear characteristics of many circuits are still …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 8–17 Read article