Journal of VLSI Design Tools and Technology
Volume 5, Issue 2 (2015)
Published
Table of contents
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Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology
Abstract: This paper proposes a review on study and analysis of an efficient fast low power 1 Kb SRAM cell using 90 and 45 nm Microwind technology. In this paper we have proposed the tentative improvement in performance parameters of SRAM cell like power dissipation, read or write speed, stability and signal to noise margin ration (SNM) using CMOS scaling.Keywords: SRAM, CMOS scaling, MicrowindCite this ArticlePathrikar A.K, Deshpande Rajkumar S. Design …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 1–3 Read article
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Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter
Abstract: Basic building block to design an analog circuit is amplifier and it is used for such applications like analog to digital and digital to analog converter, sensor network and many more. Amplifier with lofty gain and high bandwidth will increase the efficiency of design. Present time is talking about development of VLSI technology and everything is related to size of transistor and decreasing power supply in a circuit. Operational transconductance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 11–15 Read article
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4-Bit Magnitude Comparator Design using Different Logic Styles
Abstract: 4-Bit Magnitude Comparator using various logic styles is explained here. Comparison is one of the common arithmetic operations that is used to determine which number is greater, equal to, or less. Every device from OP-AMP to ALU needs to perform comparison operations. At designing level, comparator can be designed by using different logic styles. Here, comparison is done for simple 4-Bit combinational comparator and cascaded comparator which we have designed …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 16–22 Read article
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A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier
Abstract: Due to advancement of new technology in the field of VLSI, there is an increasing demand of high speed processor. Matrix multiplication is highly used in different types of computations. Speed of processor greatly depends on its multiplier (used in matrix multiplication) performance. Due to which high speed multiplier architecture become important. Several multiplication techniques have been developed to increase the efficiency of the multiplier. These techniques help in reducing …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 23–28 Read article
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Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating
Abstract: Nowadays design of electronic circuits to meet requirements like high speed, better functionality and low power is a tedious task. Power dissipation in any circuit comprises mainly two components: static power and dynamic power. The dynamic power heavily depends on the switching activity of the circuit. During the transistor switching transitions some spikes may occur, which are called as glitches. These glitches contribute 20–70% of the dynamic power and 20% …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 29–37 Read article
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Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style
Abstract: A different logic style including the constant logic style is proposed in this paper which is helpful in increasing the high speed applications. It is suitable for implementing the complicated arithmetic expressions. The objective of this paper is to reduce the delay, noised margin and power consumption. The transistor for minimal power delay product and energy delay product is proposed in this paper. The design and implementation of adder in …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 38–41 Read article
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Comparative Analysis of High Speed Comparator for A to D Converters
Abstract: In this paper dynamic comparator along with the output buffer stage has been introduced. The simulation is carried out in 130 and 90 nm technologies. The supply voltage for 130 nm is 1.3 V and for 90 nm is 0.9 V. Different analyses for various characteristics of the comparator such as ICMR, delay, offset voltage and power dissipation is carried out in 130 and 90 nm CMOS technology. The comparator …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 4–10 Read article
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Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave
Abstract: This paper focuses on I2C (Inter Integrated Circuit) protocol master controller. I2C protocol was originally given by Philips semiconductors so that faster devices can communicate with slower devices and also allow devices to communicate with each other over serial bus without data loss. The I2C controller provides support for a communication link between integrated circuits and memory units on a board. I2C is a bidirectional serial bus which contains two …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 42–48 Read article
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Automated Access Backdoor for UVM_REG Layer
Abstract: Systems on chips (SoCs) design have many configuration registers. Configuring the registers through a Bus protocol consumes lot of simulation time. Hence, time saving becomes a challenge in configuring the registers. The other way to configure registers is backdoor access. Backdoor is a zero simulation time access by mapping to the register directly using the hierarchical path. It allows rapid configuration of registers and can uncover hidden bugs as execution …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 49–53 Read article
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Characterization of High Performance Third Generation Current Conveyor using CMOS Technology
Abstract: In this paper, Conventional Third generation(CCIII) and Dual-Output Cascoded Third Generation Current Conveyor(DOCCIII) is presented. Here, both are simulated in ELDO SPICE Mentor Graphics using 90 nm CMOS technology at 0.8 V supply voltage. High performance cascoded current mirrors provide high output impedance. Third generation current conveyer has the advantages of wide current and voltage bandwidths, controlled intrinsic resistances at terminals X,Y and Z. By the use of high performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 54–63 Read article
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Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor
Abstract: This paper describes a topology of voltage follower Class-AB Voltage Follower like Translinear voltage follower using MOS and DTMOS Transistor. The circuits are simulated in 90 nm technology. The results are used to compare the performance of the above voltage followers. All analysis was supported by the simulation results. The analysis are made in terms of gain, bandwidth and transient response using ELDO spice, IC station and Design architect of …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 64–70 Read article
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Design of 8 Bit High Speed Pipelined ADC
Abstract: High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in many electronic applications. The demand for high-speed, medium resolution, low power ADCs is satisfied by various ADC architectures like folding, flsubranging, pipeline etc. Of these, pipeline architecture has proven to be the most efficient for applications such as digital communication systems, data acquisition systems and video systems. Pipelined ADC offer attractive combination of high-speed, high-accuracy and low power consumption, which …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 71–80 Read article
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Tuning Range, Phase Noise and Jitter Analysis of Current Starved Voltage Controlled Oscillator (VCO) for Digital PLL in 45 nm CMOS Technology
Abstract: A wide tuning range, low phase noise and low jitter 100 MHz Voltage-Controlled Oscillator (VCO) for DPLL was designed and implemented by 45 nm CMOS process technology using LT spice. There was a relation between the frequency tuning range, phase noise, and jitter at output of the VCO after linearizing the gain. Simulations using PTM 45 nm CMOS process technology shows, that a wide operation frequency range (tuning range) from …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 81–89 Read article