Journal of VLSI Design Tools and Technology
Volume 14, Issue 1 (2024)
Table of contents
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Exploring the Dynamics of Memristors: Mechanisms, Models, and Multifaceted Applications
Abstract: Memristors, a fundamental electronic component first proposed by Leon Chua in 1971, have garnered significant attention due to their unique electrical behavior and promising applications in various fields. This paper provides a comprehensive overview of memristors, covering their basic principles, characteristics, fabrication methods, and applications of Memristor and it’s significance with flux charge linkage. The paper also shows study of a grounded memristor emulator and it’s working as a memristor …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 1–7 Read article
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Review on to Design High Speed and Area Three Oprend Binary Adder Using MDCLCG Architecture
Abstract: The three operands binary adder is a basic function used in the creation of modular arithmetic in various algorithms, such as the pseudorandom bit generator and cryptography. The CS3A carry save adder is commonly used to perform this operation. Nevertheless, the operation's outcome delayed the transmission of O(n) because of the ripple carry step. A dual-optoic adder for parallel prefix computation, such as the Han-Carlson method, can be used to …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 14–22 Read article
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High-speed Data Converter Architectures: Latched Comparator Design & Performance Comparison
Abstract: This paper focuses on the design and optimization of latch comparators for high-speed data converter applications. The performance of different comparator architectures is compared in terms of speed, power consumption, and noise performance. The proposed latch comparator architecture uses a preamplifier to boost gain and sensitivity, and a latch to store the output signal. The latch comparator design is optimized for low power consumption and high speed, and is implemented …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 23–32 Read article
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Hardware Synchronization for Embedded Multi-core Processors
Abstract: The focus is not on whether multi-core systems are becoming prevalent, but on how microcontroller architectures should be designed to comply with stringent field requirements. This paper illustrates the transition from single to multiple cores, ensuring coherence and consistency in shared memory through hardware mechanisms. Hardware barriers are implemented to allow for point-to-point synchronization between processor cores. Practical experiments center on the initial stages of transforming single-core systems into dual-core …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 33–42 Read article
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Study and analysis of the Double Data Rate SDRAM Controller for High-speed Interfacing with Processing Device
Abstract: A real-time embedded system must now manage many programs running concurrently. Increased Data Rate Because of its burst access, speed, and pipeline features, synchronous DRAM is a typical memory-building material. DDR transfers are performed using synchronous dynamic access memory. The memory controller must be set with a pipelined design for various applications and systems to perform effectively. The purpose of this study is to design a DRAM controller that will …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 1, 2024 · pp. 8–13 Read article