Journal of VLSI Design Tools and Technology
Volume 7, Issue 1 (2017)
Published
Table of contents
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Implementation of Carry Select Adder with Reduced Area Scheme
Abstract: Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So, adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry select adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 1–5 Read article
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Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops
Abstract: This paper presents phase frequency detector using different gates like AND, NOR and NAND and comparative simulation result analysis is carried out. The simulation is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. NAND based PFD has lowest power consumption then other and it is 4.2587 µW at 1 GHz Frequency and dead zone to 18 ps which means having approximately zero dead zone problem. …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 18–28 Read article
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Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture
Abstract: Content Addressable Memory (CAM) is a storage unit used for faster accessing of lookup table that reduces processing time for search operation. It is mainly used very-high-speed searching applications like computer networking devices. The MAC address table is implemented with a CAM so that the destination port can be easily detected by reducing the switch’s latency. CAM gets its high speed of operation by parallel search mechanism. This paper proposes …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 29–34 Read article
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Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology
Abstract: This paper presents folding and interpolating ADC with resolution of 5 bit. The simulation result is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. This folding and interpolating ADC consumes less power than other, and it is 10 mW. The rate of conversion is 50 MS/S. So, it is suitable for low power application and medium resolution portable devices. Keywords: Folding ADC, interpolating, ADC, low …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 35–40 Read article
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A Novel Approach Based On-Chip High Speed Optical Interconnection Network
Abstract: On-chip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately solve the communication problem and obtain high-performance integrated circuits. On-chip interconnects are an important performance limiting factor in present day VLSI design. Performance optimization has always been a critical step in the designing of integrated circuits. In this paper, an optical interconnect in 1550 nm range is being implemented using opti-system software. A novel approach is …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 41–48 Read article
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Enhancement in RMPA Parameters using Slotted Rhombus Connected Square Shaped Antenna with Left Handed Metamaterial
Abstract: In this paper, rectangular microstrip patch antenna (RMPA) along with metamaterial which has design of “slotted rhombus connected with rectangular shaped cover structure” is proposed at height of 3.2 mm from the ground plane. The RMPA with proposed metamaterial structure is designed to resonate at 2.7 GHz frequency. This work is mainly focused on increasing the potential parameters of microstrip patch antenna. Proposed metamaterial design structure significantly reduces the return …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 49–54 Read article
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A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure
Abstract: Floor planning is a key issue in VLSI physical plan. The floor planning issue can be defined as that a given arrangement of 3D rectangular pieces while limiting reasonable cost capacities. Here, we are focusing on the minimization of the aggregate volume of 3D bite the dust. In this paper, another initial topological structure is presented utilizing weighted coordinated chart of a floor planning issue in 3D VLSI physical plan. …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 6–17 Read article