Journal of VLSI Design Tools and Technology
Volume 8, Issue 2 (2018)
Published
Table of contents
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High Gain Antenna Array (2x1 and 4x1) Design for WLAN Application
Abstract: Micro-strip antennas became very popular in 1970s primarily for space borne applications. Today they are used for government and commercial applications. These antennas consist of a metallic patch on a grounded substrate. The metallic patch can take many different configurations. However, the rectangular and circular patches are most popular because of ease of analysis and fabrication, and their attractive radiation characteristics, especially low cross-polarization radiation. In high performance aircraft, spacecraft, …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 1–8 Read article
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Characterization of Low Power-Low Jitter Digital PLL
Abstract: The architecture design is being done in transistor level and tool which supports transistor level design. Mentor Graphics Tool is used for transistor level design and its simulation design. There are few tools which support design simulation like HSpice, Spectre and PSpice. Also a foundry support is from Taiwan Semiconductor Manufacturing Corporation (TSMC) (i.e.) technology model files 180 nm from TSMC for simulation. This article presents design for 1.5 GHz …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 23–32 Read article
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Comparative Analysis of Different SRAM Cells Architecture at 70 nm
Abstract: There are severe constraints which affect the real time operation of SRAM cells. With increasing demand of device scaling, the performance parameters of SRAM cells are affected. Our main purpose is to maintain performance of memory cells in real time operation. Here, we considered three basic parameters stability, leakage current and delay for compression of various SRAM cell architectures. In this paper, we considered conventional 6T, asymmetric 7T, asymmetric 8T …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 33–41 Read article
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A Review on FPGA Parallel Architecture for Object Detection
Abstract: The main purpose in the case of present paper is to summarize the different parallel architecture techniques implemented on FPGA by which we can fulfil our requirement of object detection in image processing system. In image processing, it is difficult to find high precision and real time performance even in most powerful CPU. The various parallel architecture techniques can help in to give better performance and achieve high precision. This …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 42–48 Read article
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Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime
Abstract: The characteristics of cylindrical gate all around MOSFET have been studied in terms of the dependence of various device performance metrics on silicon film thickness (Tsi). In this work, the effect of silicon film thickness on numerous performance metrics like threshold voltage (Vt), On current (Ion), subthreshold leakage current (Ioff), On-Off current ratio (Ion/Ioff) and DIBL of cylindrical GAA are comprehensively evaluated and analysed. It has been observed that cylindrical …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 49–54 Read article
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A Review on Tunnel Field Effect Transistor for Ambipolar Suppression, Higher ON Current and a Lower Subthreshold Swing
Abstract: Modern IC technology force on the ICs design considering more area optimization and low power techniques. We study herein the effect of hetero gate dielectric materials on the OFF-current (IOFF) and ON-current (ION) of the heterogate (high-k/low-k) tunnel field-effect transistor for which the simulations give significant improvements as compared to single-gate devices using an SiO2 gate dielectric. The ambipolar behavior is suppressed and radio frequency (RF) parameters are enhanced by …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 55–66 Read article
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Area and Power Improvement with New Initial Ordering Method Combined with Sift Algorithm for BDD Mapped Circuits
Abstract: Digital circuits are the important elements in almost every electronic design. As the size of electronic ICs are shrinking rapidly, the minimization of the circuit elements and power consumption became more focused area of VLSI research. In this paper, we have introduced a new method for reduction of area and power of binary decision diagram mapped circuits. Binary decision diagrams are used to represent digital functions in VLSI CAD. It …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 67–71 Read article
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A Common Mode Scan Based BIST for Stuck-at-Fault and Path Delay Fault
Abstract: Testing for delay and stuck-at faults requires two pattern tests and test sets are usually large. Built-in self-test (BIST) scheme is attractive for comprehensive testing. The BIST test pattern generators (TPGs) for such testing should be designed to ensure high pattern-pair coverage. In the proposed work, necessary and sufficient conditions to ensure complete/maximal pattern-pair coverage for sequential circuit have been derived. A new test data-compression scheme is an effective approach …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 72–78 Read article
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Design of Three-Stage Pipelined Floating Point Arithmetic Operators
Abstract: Some embedded systems perform signal processing operations (Fourier transform, filtering) as for example for the recognition voice, high quality audio and control of critical systems (airplane, rocket). This type of operation may require the use of floating numbers. This paper presents the hardware implementation of floating point arithmetic operators for addition, subtraction, multiplication using the IEEE-754 single precision format. Proposed architecture follows two different RTL approach, Melay FSM and multiplexer …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 9–22 Read article