Journal of VLSI Design Tools and Technology
Volume 6, Issue 2 (2016)
Published
Table of contents
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Challenges Beyond 100 nm MOS Devices
Abstract: MOS devices have been aggressively scaled down in research and in the production in last few years. Sub-100 nm feature size MOS circuits have been used for many. However, many serious limitations and problems emerged with such a small geometry MOSFETs are used to realize very large-scale integrated circuits. Commercial 45 nm technology node, has much higher production cost and it is one of the greatest concern for scaling down …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 1–4 Read article
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Functional Verification of AMBA AHB-Lite using Layered Testbench Technology of System Verilog
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single system on chip (SoC) makes verification of any SoC based design very critical. Ever increasing complexity and size of designs lead to a number of verification challenges, which are the productivity, efficiency, reusability and completeness. About 75–80 % of the total design cycle time is spent in functional verification. To …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 104–112 Read article
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Layout Design, Fabrication and Characterization of n-Channel MOSFET
Abstract: Primary force behind evolution of semiconductor industry is MOSFET, after its first IC based experimental demonstration in 1960s. It is fundamental working unit of most of the electronic circuits like cells in living being. Number of devices on a single chip has been increased with rapid phase with evolution of new technology of materials. Today there are more than 4 billion transistors are there on a single chip with effective …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 13–18 Read article
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Comparative Analysis of MOSFET, CNTFET and NWFET for High Performance VLSI Circuit Design: A Review
Abstract: Nanowires are inimitable materials for considering phenomenon in nanoscale regime. Nanowires development exhibits ample of applications by controlling their, structure, composition as well as their electrical properties. This paper review diverse types of nanowires, nanowire field-effect transistor (NWFET) structure and their comparison with novel devices. Firstly, this paper describes different types of nanowires and nanowire heterostructure that shows nanowire heterostructures eliminates various factors that limit the performance of homogeneous nanowire …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 19–32 Read article
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Design and Implementation of Low Power 8-bit Level Crossing ADC
Abstract: Implantable medical devices, electronic gadgets, wireless communication elements and many other such applications require low power electronic circuits. Analog to digital converters are essential part of most of such circuits. This paper presents a design of the level crossing analog to digital converter (LC-ADC) architecture. The proposed circuit and layout has been implemented in semi-conductor laboratory (SCL) 180 nm technology and its performance was evaluated using cadence virtuoso at supply …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 33–43 Read article
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Design and RTL Implementation for AHB-APB Bridge on SoC
Abstract: The focus of this research is to design and implement an interconnection protocol with 32-bit read/write data which operates on AMBA AHB-APB bridge. With the advent of scaling technology, embedded system focuses more on low-power dissipation and SoCs. Hence processors and routing protocols which focus on low-power design by ARM have gained popularity. In high-speed communication modules, the protocol works efficiently but has limitations with device operating at low speed. …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 44–52 Read article
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Design and Performance Trends of Low Power Sigma-Delta A/D Converters
Abstract: Analog-to-Digital Converters (ADCs) act as the bridge linking the real world and the digital world, i.e., they can covert the analog signal to the digital signal, and hence benefit to the storage, processing and transmission of the data. This paper presents a first of its kind study on the various Sigma-Delta (ΣΔ) ADC architectures proposed to achieve low power consumption and their performances have been compared with respect to the …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 5–12 Read article
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Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique
Abstract: This paper enumerates the design of low power shift registers using dual-edge triggered flip-flop (DETFF). In the conventional shift registers, high leakage current is becoming a significant contributor to power dissipation. In order to overcome this problem, the multi-threshold complementary metal oxide semiconductor (MTCMOS) technology is used for leakage minimization in proposed designs. This technology features both low-threshold and high-threshold voltage MOSFETs. High-threshold voltage MOSFETs reduced the standby leakage current …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 53–61 Read article
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Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM
Abstract: Huge complexity of chip increased in the past recent years and integration of more number of transistors on a single SoC makes verification of any SoC based design very critical. About 75–80% of the total design cycle time is spent in functional verification. To reduce this time and effort, hardware verification languages came into picture. The most popularly used HVL is system verilog, which is based on object oriented programming …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 62–73 Read article
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A New TGC-Differential Input Stage to Modify Dynamic Comparator
Abstract: As the technology rapidly scaling down, the escalating demand for higher accuracy is putting a heavy pressure to find ways to get rid of one of the major issues among present day dynamic comparators i.e. random offset voltage generation. A number of offset calibration techniques have been presented to resolve this issue. It has become an important concern to analyze these techniques for scaled down technology nodes to cop up …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 74–85 Read article
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Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power
Abstract: This paper presents the analysis and characterization of various topologies of dynamic latch based complementary metal oxide semiconductor (CMOS) comparator. Various comparator topologies like resistor divider comparator (RDC), differential pair comparator (DPC), double-tail dynamic latched comparator (DTDLC), energy efficient two-stage comparator (ETWC) and two-stage dynamic comparator (TSDL) are analyzed and compared for various performance parameters. Besides zero static power consumption, resistor divider comparator has high offset voltage and it depends …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 86–98 Read article
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Implementation and Simulation of High-Speed Dynamic Latch Comparator for ADC
Abstract: As per emerging issues in analog-mixed signal (AMS) design towards high-speed and low power, limits the performance of high-speed applications. Circuit complexity, speed, offset voltage and resolutions are essential parameter of comparator that affects the analog-to-digital converter (ADC) performance. Based on specifications, to achieve lower offset voltage and higher load drivability of latched comparator is presented. Moreover, the circuit is able to reduce power dissipation as the topology is based …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 99–103 Read article