Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique

archana kumari; navdeep prashar

doi:10.37591/jovdtt.v6i2.2987

Abstract

This paper enumerates the design of low power shift registers using dual-edge triggered flip-flop (DETFF). In the conventional shift registers, high leakage current is becoming a significant contributor to power dissipation. In order to overcome this problem, the multi-threshold complementary metal oxide semiconductor (MTCMOS) technology is used for leakage minimization in proposed designs. This technology features both low-threshold and high-threshold voltage MOSFETs. High-threshold voltage MOSFETs reduced the standby leakage current during the sleep mode. The conventional and proposed shift registers are presented and compared. The result shows a significant reduction in power as compared to the conventional shift registers. The shift register has been designed and simulated by using Tanner v13.0 tools. Keywords: Shift register, dual-edge triggered, flip-flop, low power, multi-threshold CMOS