Journal of VLSI Design Tools and Technology
Volume 6, Issue 1 (2016)
Published
Table of contents
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A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit
Abstract: Modified constant delay logic style and clocked logic style is defined by comparing their result. In this paper, a design technique has been proposed which reduces the power dissipation. The design and implementation of full adder and ripple carry adder with constant delay logic. The leakage power has become a serious concern in CMOS technologies that has been solved by the MCD and clocked logic style. Constant delay logic style …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 1–5 Read article
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A Review for Power Optimization in MOS Devices using Different Logic Styles
Abstract: This paper presents power optimization in MOS devices by using different logic styles which is helpful for increasing high speed application. The simulation process can be done in different CMOS technologies and performance parameter of power is compared for different logic styles. Full adder and ripple carry adder are mostly used to define different logics to optimize the power. Constant logic style provides the low power and different logic style …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 16–20 Read article
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Simulation Study of Tapered Shape FinFET
Abstract: During recent years, nonplaner tri-gate (TG) field-effect transistors (FETs) such as FinFETs have been extensively studied for the enhancement of electrostatic control and suppression of short-channel effects (SCEs) in the sub50 nm regime. As the device scaled, it is observed that the shape of the rectangular FinFET becomes tapered shape. This paper presents the design and analysis of a tapered-shaped FinFET. By varying the sidewall inclination angle of a rectangular …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 21–31 Read article
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Switched Capacitor-based RC Filter
Abstract: Today we know that the demand of low voltage for low power integrated circuits (ICs) are used for growing the portable equipment in all the markets including telecommunication, computers and customer electronics with smaller size. The low voltage need for ICs is also motivated by the new dip submicron complementary metal oxide semiconductor (CMOS) technology scaling that required all transistors of smaller size. In current years, a lot of researches …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 32–40 Read article
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Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell
Abstract: The demand of high density VLSI circuits has been increasing as the size of ICs is becoming small day by day. It has been seen that, to reduce active power dissipation in memory, the supply voltage reduction is necessary. Lowering the supply voltage is one of the most straightforward and effective ways to suppress the energy consumption because reducing the supply voltage could reduce the dynamic power and leakage power …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 41–48 Read article
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Design of Single Bitline Novel 5T SRAM Cell to Reduce The Power Dissipation Using Cadence
Abstract: Fast growing field of IC technology is persistently demanding for low power consumption and efficient solution. Most of the available SRAM designs are based on standard 6T SRAM cell in addition to other circuit and transistors count. A novel 5T CMOS SRAM is presented in this paper, for simultaneously minimizing power consumption and an improving process speed. The presented unique 5T SRAM cell employs single bitline for read/write function. Implementation …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 49–54 Read article
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Implementation of Edge Detection Algorithm on FPGA using Hardware Software Co-simulation
Abstract: Image processing is one of the most booming research areas in modern days. Every modern device incorporates image processing in one or the other way. Most of the image processing algorithms start with basic edge detection. The performance of the edge detection can be improved using state of art FPGA devices. Implementation using field programmable gate arrays (FPGA) speeds up the processing of edge detection algorithms. The paper discusses the …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 55–61 Read article
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Hardware Implementation of Configurable Multi Image Fusion
Abstract: Multifocus images make it difficult to describe a scene accurately. Hence, the fusion of two or more images forms a good solution in order to obtain a new image containing more appropriate description of the scene than any of the input images. This paper presents a method of image fusion which uses stationary wavelet transform and fuzzy logic. By overcoming the disadvantages of discrete wavelet transform such as downsampling and …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 6–15 Read article
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Modeling of Voltage Buffer and Memristor Voltage Buffer Using 180 nm Technology
Abstract: Objective of this paper is the analysis of voltage buffer and is referred to as a common drain amplifier or that can be considered as a source follower also. It compares the result of simple voltage buffer that results with the memristor inbuilt in the same schematic circuit of voltage buffer. Memristor is considered as a fourth existing component after the resistor, capacitor and an inductor proposed by Dr. L.O. …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 62–72 Read article
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Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell
Abstract: VLSI design is persistently demanding for ultra-low power efficient and data stability solution. This review paper studies and analyses about various techniques to reduce leakage and dynamic power dissipation. Sleepy keeper approach, super cutoff mode, NTC method, dual-threshold approach, quiet-bitline and single bitline architecture are discussed for the power reduction. Sleepy keeper, NTC and dual-threshold approach are focused for high data stability and performance. Quite bitline architecture SRAM saves overall …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 73–77 Read article
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GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology
Abstract: Carry select adder (CSLA) is an efficient adder used in modern processors. But, the CMOS logic implementation at the transistor level makes it complex. The use of smaller transistor size has shrunk the overall design but the transistor count was retained. Hence, in this paper the transistor level implementation of variable sized CSLA architecture is done using gate diffusion input (GDI) logic. This implementation drastically simplifies the CSLA in terms …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 78–88 Read article
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A Differentiator Based on Second Generation Current Controlled Conveyor
Abstract: A new second generation current controlled conveyor (CCCII) with programmable gain at output terminal ‘Z’ is presented in this paper. The inherent advantages of the proposed circuits are low supply voltage requirement of ±0.85 V, small input parasitic resistance in the range of 29.12 Ω–297.71 Ω for a current range of 10 µA–300 µA, low power dissipation of 79.39 µw and low DC current error of 0.068%. The proposed CCCII …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 89–95 Read article