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27 articles for “Arithmetic Circuit”
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Design of a Multipurpose Ternary Arithmetic Circuit Using CNTFET
Abstract: AbstractIn this paper, a multipurpose ternary arithmetic circuit is presented for ternary processors based on carbon nanotube field effect transistors (CNTFETs). Both addition and subtraction can be performed using same circuit’s configuration, which is the special feature of the proposed circuit. The combination of pseudo and complimentary logic structure are employed to blend the binary and ternary logic techniques. The propagation delay and power delay product are 139.5 pico second …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 1, 2016 · pp. 13–24 Read article
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A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology
Abstract: In CMOS logic circuits, the reduction in the threshold voltage due to voltage scaling leads to increase in the subthreshold leakage current and hence static power dissipation. Although power consumption is important for modern VLSI design, operation speed and occupied area are still the main requirements of the VLSI design. Multi threshold voltage CMOS (MTCMOS) technology is a good solution which provides a high performance and low-power design without any …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 1–7 Read article
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Design and Implementation of Carry Select Adder based On Wallace tree Multiplier using Adiabatic Logic
Abstract: The Wallace tree multiplier construction using a carry select adder (CSA) and this paper discusses adiabaticlogic. The proposed design aims to reduce power consumption while maintaining high performance.Adiabatic logic is employed to reduce power dissipation by recycling energy during the logic transitions. TheWallace tree multiplier is used to perform fast multiplication of two large numbers by breaking down themultiplication process into smaller sub-tasks. The CSA is used as the adder …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 21–31 Read article
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Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
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Improvement of Design Issues in FinFET based Design Techniques for XOR and XNOR Circuits at 45 nm Technology
Abstract: The scaling of conventional CMOS circuit inclines to the short channel effect due to leakage current increase in the circuit. To minimize the short channel effect, FINFET can be used in place of conventional CMOS circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. This paper assesses and compares the performance of XOR and XNOR logic circuits. This …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 22–35 Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 42–54 Read article
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Implementation of Carry Select Adder with Reduced Area Scheme
Abstract: Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So, adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry select adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 1–5 Read article
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A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit
Abstract: A size and power efficient current-mode decimal adder is proposed in this paper. The proposed adder does not use binary coded decimal (BCD) number system for processing the decimal data like other decimal adders. Instead, it processes the decimal data as the actual decimal inputs. The proposed adder can be used as a decimal half adder as well as a decimal full adder. The adder is based on simple decimal …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 18–23 Read article
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Modelling and Electrical Characterization of Single Electron Transistor
Abstract: A nano-electronic device with low power consumption, high performance, and quantum effects is the single electron transistor (SET). It's used in charge sensor applications, infrared radiation detectors, and spectroscopy. However, it faces limitations in lithography, co-tunneling effect, low gain, high output impedance, and background charges. Therefore, prior simulation is needed to optimize SET's work function and understanding physics concepts. A master equation approach is used to propose a new model …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 3, 2024 · pp. 19–25 Read article
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Spintronic Logic Circuits for Ultrafast Processing
Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article
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Study And Literature Analysis of The Coarse-Grained Logic Interface with Floating-Point Arithmetic Unit
Abstract: Field-Programmable Gate Arrays (FPGAs) have become an essential digital circuit implementation techni que. The research looks at the design parameters by evaluating the building of an arithmetic logic unit (ALU) in Xilinx Vivado utilizing Hardware Description Language (HDL) and implementing common Field Programmable gate arrays (FPGAs). The ALU is a logic design component in digital computers that seeks to deliver optimal algorithms to maximize the usage of available hardware. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 45–55 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
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A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic
Abstract: This paper presents a method to designing Various Adder Circuits using CMOS Logic Style for Energy-Efficient Arithmetic Applications. We present Ripple Carry Adder, Carry Bypass Adder, Carry Look Ahead Adder and Carry Skip Adder in CMOS logic styles that lead to have reduced power-delay product (PDP). We executes a comparison against each other adders which finally provide result as having a low PDP, with reference to power consumption, speed and …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 2, 2021 · pp. 24–34 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute-intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered by …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 2, 2022 · pp. 22–33 Read article
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Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level
Abstract: Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 10–18 Read article
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Design of FPGA Based ALU Using Reversible Logic Gates
Abstract: Reversible or information misfortune less circuits has applications in computerized signal handling, correspondence, PC design and nanotechnology. Reversible technique is utilized to minimize heat that happens in traditional circuits by keeping the loss of data. This paper proposes a reversible configuration of an ALU. This ALU comprises of eight operations, five are of arithmetic category and three are from logical category operations. An arithmetic operations incorporate add, sub, increase by …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 3, 2016 · pp. 15–21 Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article
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A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture
Abstract: A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 37–46 Read article
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Implementation and Analysis of Linear Electrical Networks using Interval Arithmetic on FPGA’s
Abstract: Interval arithmetic provides better method for monitoring and controlling errors in scientific calculations. Interval arithmetic can be used to obtain an analysis of linear electrical networks using hardware description language (HDL). In this paper the mean value theorem is used to analyze the circuits and implemented on hardware. The mean value theorem is applied for three different circuits i.e., for first order, second order and third order analog circuits. The …
Published in Current Trends in Signal Processing · Vol. 4, Issue 3, 2014 · pp. 14–21 Read article