International Journal of VLSI Circuit Design & Technology

Latest articles

• Published Subscription Review Article 26 May 2026

  An Overview on VLSI based Hardware Security in IoT Node

  By Kazi Kutubuddin Sayyad Liyakat, Heena Shaikh, Dr. Kosgiker G M

  Abstract: In the coming era, security will not be a feature we add to an IoT device; it will be a property inherent to its transistor-level design. By encoding security into the VLSI architecture, we move away from the fragile "software-only" paradigm and toward a future where the identity of the device is as immutable as the laws of physics. The rapid proliferation of Internet of Things (IoT) devices has transformed …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article →

• Published Subscription Review Article 15 May 2026

  A Comprehensive Review of CMOS Analog Circuit Design Techniques for Low-Power VLSI Systems

  By Heena T Shaikh, Kazi Kutubuddin Sayyad Liyakat

  Abstract: CMOS analog circuit design plays a significant role in the development of modern low-power Very Large-Scale Integration (VLSI) systems used in wireless communication, biomedical devices, portable electronics, embedded systems, and Internet of Things (IoT) applications. Research on low-power CMOS analogue design methodologies has intensified because to the growing need for high-performance, small, and energy-efficient electronic products. However, reducing power consumption while maintaining signal accuracy, noise performance, stability, bandwidth, and overall …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article →

• Published Subscription Review Article 15 May 2026

  Machine Learning Assisted Timing Violation Prediction in Sub-7nm VLSI Physical Design

  By Rosalin Pradhan, Bibhu Prasad Ganthia

  Abstract: The continuous scaling of semiconductor technology into the sub-7nm regime has introduced significant challenges in timing closure due to process variability, interconnect delay, power density, and manufacturing uncertainties. Conventional static timing analysis techniques often require extensive computational resources and iterative optimization cycles, resulting in increased design complexity and longer turnaround time. This research proposes a Machine Learning Assisted Timing Violation Prediction framework for sub-7nm VLSI physical design to improve early-stage …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article →

• Published Subscription Review Article 15 May 2026

  Spintronic Logic Device Modeling and Energy Optimization for Beyond-CMOS Computing Systems

  By Bibhu Prasad Ganthia, Rosalin Pradhan

  Abstract: The continuous scaling limitations of conventional CMOS technology have accelerated the exploration of alternative computing paradigms for next-generation low-power and high-performance systems. Spintronic logic devices have emerged as a promising solution due to their non-volatility, ultra-low switching energy, high integration density, and compatibility with beyond-CMOS architectures. This research presents a comprehensive modeling and energy optimization framework for spintronic logic devices applied in beyond- CMOS computing systems. The proposed work investigates …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article →

• Published Subscription Review Article 5 May 2026

  64 Bit ALU DESIGN USING VEDIC MATHEMATHICS

  By Sirigineedi Mounisha, Uppalapati Joshna Venkata Srujana, Vemula Rajesh, Velugubanti Lakshman, Yepuganti Manikanta, I.Rama Satya.Nageswara Rao, Saran Kumar

  Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article →

• Published Subscription Review Article 31 Dec 2025

  How small circuits power big technology in the world of VSIL

  By V. Basil Hans

  Abstract: Very Small Integration Level (VSIL) circuit technology represents an emerging class of ultra- compact, low-power electronic design methodologies that enable the creation of highly efficient and scalable systems. This article explores the fundamental principles behind VSIL circuits, including device miniaturization, optimized layout strategies, adaptive power management, and noise-resilient architectures. We also look into the methodical engineering of VSIL circuits to satisfy the ever-tougher performance, robustness, and long- term energy-efficiency demands …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 44–53 Read article →

• Published Subscription Original Research 31 Dec 2025

  Spintronic Logic Circuits for Ultrafast Processing

  By Vaibhav Godase, Shilpa Shinde

  Abstract: Spintronic logic has emerged as one of the most promising post-CMOS paradigms capable of addressing the speed, density, and energy challenges of deeply scaled silicon technologies. By relying on the intrinsic properties of electron spin and magnetization dynamics, spintronic devices—particularly Magnetic Tunnel Junctions (MTJs), Spin-Transfer Torque (STT), and Spin–Orbit Torque (SOT) structures—enable ultrafast, non-volatile data processing with significantly reduced energy consumption. Despite remarkable device-level advancements, circuit- level realization of high-speed, …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 35–43 Read article →

• Published Subscription Original Research 31 Dec 2025

  Optimized Hardware Realization of AES for High-Throughput FPGA Platforms

  By Altaf Osman Mulani

  Abstract: The Advanced Encryption Standard (AES) is the predominant symmetric-key cryptographic algorithm used for securing digital communication across embedded systems, IoT devices, cloud infrastructures, and defense networks. Although software-based AES implementations offer flexibility, they often fail to meet the high-speed, low-latency, and energy-efficient requirements of modern real-time applications. Reconfigurable hardware platforms such as Field-Programmable Gate Arrays (FPGAs) provide a powerful alternative by enabling architectural customization, intrinsic parallelism, and optimized hardware acceleration. …

  Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 11–22 Read article →

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