International Journal of VLSI Circuit Design & Technology
Volume 4, Issue 1 (2026)
Table of contents
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64 Bit ALU DESIGN USING VEDIC MATHEMATHICS
Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Spintronic Logic Device Modeling and Energy Optimization for Beyond-CMOS Computing Systems
Abstract: The continuous scaling limitations of conventional CMOS technology have accelerated the exploration of alternative computing paradigms for next-generation low-power and high-performance systems. Spintronic logic devices have emerged as a promising solution due to their non-volatility, ultra-low switching energy, high integration density, and compatibility with beyond-CMOS architectures. This research presents a comprehensive modeling and energy optimization framework for spintronic logic devices applied in beyond- CMOS computing systems. The proposed work investigates …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Machine Learning Assisted Timing Violation Prediction in Sub-7nm VLSI Physical Design
Abstract: The continuous scaling of semiconductor technology into the sub-7nm regime has introduced significant challenges in timing closure due to process variability, interconnect delay, power density, and manufacturing uncertainties. Conventional static timing analysis techniques often require extensive computational resources and iterative optimization cycles, resulting in increased design complexity and longer turnaround time. This research proposes a Machine Learning Assisted Timing Violation Prediction framework for sub-7nm VLSI physical design to improve early-stage …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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A Comprehensive Review of CMOS Analog Circuit Design Techniques for Low-Power VLSI Systems
Abstract: CMOS analog circuit design plays a significant role in the development of modern low-power Very Large-Scale Integration (VLSI) systems used in wireless communication, biomedical devices, portable electronics, embedded systems, and Internet of Things (IoT) applications. Research on low-power CMOS analogue design methodologies has intensified because to the growing need for high-performance, small, and energy-efficient electronic products. However, reducing power consumption while maintaining signal accuracy, noise performance, stability, bandwidth, and overall …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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An Overview on VLSI based Hardware Security in IoT Node
Abstract: In the coming era, security will not be a feature we add to an IoT device; it will be a property inherent to its transistor-level design. By encoding security into the VLSI architecture, we move away from the fragile "software-only" paradigm and toward a future where the identity of the device is as immutable as the laws of physics. The rapid proliferation of Internet of Things (IoT) devices has transformed …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article