STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of VLSI Design Tools and Technology

Design and Implementation of Carry Select Adder based On Wallace tree Multiplier using Adiabatic Logic

  1. K. Madhava Rao
  2. T. Nikitha
  3. S. Shyam Sundar
  4. Sarapu Nithish Chary
  5. M. Rohith Kumar Reddy

Abstract

The Wallace tree multiplier construction using a carry select adder (CSA) and this paper discusses adiabaticlogic. The proposed design aims to reduce power consumption while maintaining high performance.Adiabatic logic is employed to reduce power dissipation by recycling energy during the logic transitions. TheWallace tree multiplier is used to perform fast multiplication of two large numbers by breaking down themultiplication process into smaller sub-tasks. The CSA is used as the adder to improve the performance ofthe multiplier by reducing the propagation delay. The proposed design is simulated using a 90nm CMOSprocess and the results show that the adiabatic Wallace tree multiplier using CSA achieves a significantreduction in power consumption while maintaining high performance. This design is suitable for applicationsthat require high-speed multiplication with low power consumption, such as digital signal processing,graphics processing, and cryptography.

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