A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic

Pinaki Satpathy; Santanu Maity

Abstract

This paper presents a method to designing Various Adder Circuits using CMOS Logic Style for Energy-Efficient Arithmetic Applications. We present Ripple Carry Adder, Carry Bypass Adder, Carry Look Ahead Adder and Carry Skip Adder in CMOS logic styles that lead to have reduced power-delay product (PDP). We executes a comparison against each other adders which finally provide result as having a low PDP, with reference to power consumption, speed and area. All the full-adders were constructed with a 90 um CMOS technology, and were basically examine using a comprehensive test bench that allowed quantify the current taken from the full-adder inputs, besides the current provided from the power supply. Post-layout simulations show that the proposed full-adders outperform its counterparts exhibiting an average PDP advantage of 80%, with only 40% of relative area.