STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of VLSI Design Tools and Technology

Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level

  1. Charan Ukku
  2. Dhanunjaya Karumanchi
  3. Venkatachalam K.

Abstract

Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the schematic of these basic gates is first designed and then a symbol is created concerning the schematic designed. The simulation is going to be done for the 4-bit multiplication operation. And the preferred technique is designed and simulated using LT spice XVII at 22nm technology.

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