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193 articles for “A transistor”
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Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort and Transistor Sizing
Abstract: With logical effort minimum delay of the path can be estimated by only knowing number of stages, path effort, and parasitic delay without the need to assign transistor sizes. This is superior to simulation where delay depends on sizes and you never achieve certainty that the size selected would offer minimum delay. In this work 3 cascaded inverters is being sized in the ratio 1:2:3 to achieve minimum propagation delay …
Published in Journal of VLSI Design Tools and Technology · Vol. 2, Issue 1-2-3, 2012 · pp. 29–31 Read article
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Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability
Abstract: The demand of static random access memory cell in embedded memories is rapidly increasing. To design SRAM is continuously becoming difficult due to limitation of weaker write margin, degraded data stability and higher leakage power consumption. In order to overcome these limitations, new 8T SRAM has been explored. The simulation results depicts better data stability, low access delay and decreased leakage power consumption. Alternatively, proposed cell with sleep transistor and …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 35–44 Read article
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Polypyrrole-Based Conductive Polymer-Gated Single Electron Transistor with Deep Neural Network Assistance for Biomedical Energy Harvesting and Charge Detection
Abstract: The increasing demand for intelligent biomedical monitoring systems has accelerated research into ultra-low-power sensing technologies capable of operating with high sensitivity and minimal energy consumption. Conductive polymers have attracted considerable attention for biomedical and nanoelectronic applications due to their tunable electrical properties, biocompatibility, and environmental stability. Among them, Polypyrrole (PPy) is a promising functional polymer that can enhance charge transport and electrostatic coupling in nanoscale devices. In this work, a …
Published in Journal of Polymer & Composites · Vol. 14, Issue 4, 2026 Read article
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An overview of Nanocrystalline Hydrogenated Silicon Thin film Transistor
Abstract: This article elaborates and comprehends an overview on nc-Si:H TFT's, detailing and highlighting the topics like fabrication methodology, properties/stability, modelling, characterization techniques, challenges and futuristic scope/applications.With the growing demands in commercialization of Solar Cells (low-cost photo voltaic devices), Large Area Displays (like OLED’s), Thin film electronics (FPD applications), pixel switches, wearable/flexible electronics and so on, has prompted researchers to develop nc-Si:H TFT's (an alternative solution) which can out perform the …
Published in Nano Trends – A Journal of Nano Technology & Its Applications · Vol. 27, Issue 2, 2025 · pp. 1–23 Read article
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Design and Verification of Low Power High Speed Voltage Level Shifter Based on Pass Transistor Methodology
Abstract: This study explains how a voltage level shifter (LS) can be built using a Wilson current mirror level shifter (WCMLS) with a mirrored output. The proposed fix avoids WCMLS's typical issue of requiring a mirror with a size ratio that is too large. It's a space- and cost-saver. The proposed LS requires less components than its modern versions and uses only tiny components, taking up even less space. The proposed …
Published in Journal of Control & Instrumentation · Vol. 14, Issue 2, 2023 · pp. 30–37 Read article
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GDI Logic Implementation of Variable Sized CSLA Architectures Using 45 nm SOI Technology
Abstract: Carry select adder (CSLA) is an efficient adder used in modern processors. But, the CMOS logic implementation at the transistor level makes it complex. The use of smaller transistor size has shrunk the overall design but the transistor count was retained. Hence, in this paper the transistor level implementation of variable sized CSLA architecture is done using gate diffusion input (GDI) logic. This implementation drastically simplifies the CSLA in terms …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 1, 2016 · pp. 78–88 Read article
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Impact of Work Function Variations on Data Stability of FinFET based 6T SRAM Cell
Abstract: The performance of FinFET SRAM cell is severely affected due to metal gate work function variations (WFV) in FinFET device. In order to provide guidelines for SRAM cell optimization, it is essential to examine the data stability due to the contribution of each cell transistor from WFV point of view. In this work, we investigate the effect of VTH variations of each transistor of tri-gated FinFET 6T SRAM cell on …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 2, 2021 · pp. 1–13 Read article
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A Comprehensive Review on FinFet Technology : Advantages, Challenges and Applications
Abstract: New devices and enhanced layers have been developed, specially the FinFET (Fin Field-Effect Transistor) which is considerably superior to the planar transistor because of its ability to meet the new demands of systems for high-performance, low-power, and dimensions reduction. Some of the recent developments in FinFETs mentioned in this review include a reduction of leakage currents by 50% and an enhancement of the speed by 30%; thus, FinFETs remain fundamental …
Published in Journal of Semiconductor Devices and Circuits Read article
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Design and Implementation of Low Power Area Effective 2×4 Decoder for SARM Applications Using 16 nm Technology.
Abstract: This project involves analysis of Modified Mixed Logic Design abbreviated as MMLD which includes following design logics: Complementary Metal Oxide Semiconductor abbreviated to CMOS logic design, Gate Diffusion Input abbreviated as GDI technique, and Dual Value Logic called as DVL. Two logic styles are used in this paper study to reduce power dissipation and delay time which are fourteen 14-transistor and fifteen 15-transistor decoders. Every situation requires the use of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 10, Issue 1, 2024 · pp. 24–36 Read article
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Numerical Simulation-based Comparative Study of P3HT-based Top Contact and Bottom Contact OTFTs
Abstract: AbstractIn this paper presents numerical simulation-based comparative study of bottom and top contact configurations of P3HT based organic thin-film transistor (OTFT). I-V characteristics has been evaluated using the TCAD simulator and comparison of the performance parameters of these devices has been presented. The dimensions of the transistors for all the proposed structures are kept the same for a valid comparison between them. The observed results were explained based on the …
Published in Journal of Electronic Design Technology · Vol. 10, Issue 3, 2019 · pp. 27–32 Read article
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Electro Thermal Simulation of AlGaN/GaN HEMT
Abstract: This paper presents electro thermal simulation of AlGaN/GaN High Electron Mobility Transistor (HEMT) without AlN layer nucleation layer and AlGaN/GaN HEMT by introducing AlN nucleation layer. With the help of Silvaco ATLAS lattice temperature of the devices figured out. It is observed that self heating in AlGaN/GaN HEMT without AlN nucleation layer is higher than the self heating in AlGaN/GaN HEMT with AlN nucleation layer. Simulation of lattice temperature inside …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 2, 2019 · pp. 18–27 Read article
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Physics of Semiconductors and Electronic Circuits
Abstract: This study talks about the basic ideas behind semiconductor physics and how important they are for making and running modern electronic circuits. It starts with a look at intrinsic and extrinsic semiconductors, going into how charge carriers move, energy band theory, and how doping affects how well the electricity flows. Next, the conversation turns to semiconductor devices like diodes, bipolar junction transistors (BJTs), and field-effect transistors (FETs). The focus is …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 9–17 Read article
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Analysis and Characterization of Circuits for Leakage Power Reduction at Sub-50 nm in CMOS Circuits
Abstract: This paper analyzes various techniques to decrease leakage power in complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) circuits, because due to continuous scaling of CMOS technology there is improvement in speed of semiconductor devices and the side effect of this scaling is leakage power. With the development of technology in CMOS VLSI Circuit, length of transistors has been reduced and speed of operation is increasing simultaneously. As …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 2, 2022 · pp. 11–22 Read article
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High Speed and Low Power Basic Digital Logic Gates, Half-Adder and Full-Adder Using Modified Gate Diffusion Input Technology
Abstract: In this paper, modified gate diffusion input (MGDI) technology has been used for the design and implementation of digital integrated circuits (ICs). In today’s digital world, IC plays a vital role in high-performance computing, communication, and many consumer electronics. IC manufacturing technology has scaled down to smaller device dimensions. This scaling has a great impact on the design of digital ICs. The main objective of the IC manufacturing technology is …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 1, 2018 · pp. 34–42 Read article
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Dynamic Comparators for Very High-Speed ADC’s
Abstract: The need for ultra- low power and space economical analog –to- digital converters (ADCs) is pushing towards the utilization of low voltage CMOS dynamic comparators to maximise the facility potency and speed. the traditional dynamic comparators have options like high input ohmic resistance, no static power dissipation and sensible strength against noise and couple. the downside is that giant numbers of transistors are accustomed minimize the offset, therefore the speed …
Published in Recent Trends in Fluid Mechanics · Vol. 8, Issue 3, 2021 · pp. 32–45 Read article
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An Automatic Upper/Dipper Light control circuit for vehicle
Abstract: A few vehicles on streets are expanding step by step, likewise, the innovation has grown however the wellbeing factor is constantly required to have been thought of. These days vehicles come warmed with loads of wellbeing highlights. One of the fundamental wellbeing highlights that should be introduced is a programmed upper scoop control of the fog light, this component can principally be utilized during evening driving. Natural eyes are extremely …
Published in Trends in Opto-electro & Optical Communication · Vol. 13, Issue 2, 2023 · pp. 25–31 Read article
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A Comprehensive Review of FinFet Technology: Advantages, Challenges and Applications
Abstract: This has been complemented by improvements on the new layers that have surpassed the manufactures planar transistor by the new FinFET (Fin Field-Effect Transistor), which enhance modern demands on high performance, small size and low power consumption. This review is for a timely information on the latest development on FinFET technology, such as by curbing leakage currents by 50 percent and enhancing its speed by 30 percent proving that FinFETs …
Published in Journal of Semiconductor Devices and Circuits · Vol. 11, Issue 3, 2024 · pp. 1–12 Read article
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Development of Polymer Based SRAM Cell with Enhance Low Power Performance
Abstract: Low-power memory technologies are in high demand with the rapid growth of portable electronics and energy-efficient computing systems. Static random-access memory (SRAM) plays a crucial role in processors, cache memories, and system-on-chip applications due to their speed and reliability. Static Random Access Memory (SRAM) is typically implemented using complementary MOS (CMOS) technology, which integrates both PMOS (P-channel Metal–Oxide–Semiconductor) and NMOS (N-channel Metal–Oxide–Semiconductor) transistors. However, as technology scales to deep submicron …
Published in Journal of Polymer & Composites · Vol. 14, Issue 1, 2026 · pp. 1439–1448 Read article
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Low Power Area Efficient 4×4 Vedic Multiplier using GDI half adders with Better Delay Performance
Abstract: In the field of VLSI, wireless communication and digital signal processing, low power and area efficient architectures are considered. Majority of such applications uses multiplication. The multiplication is done using repetitive addition and shift and add method. It consumes more area delay and power. Vedic multiplier is one of the efficient multiplier. It is designed using different Vedic techniques or sutras, which reduces the area, power consumption and provide better …
Published in Journal of Control & Instrumentation · Vol. 10, Issue 2, 2019 · pp. 28–39 Read article
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The Evolution of Digital Integrated Circuits: A Journey Through Technological Advancements
Abstract: The evolution of digital integrated circuits (ICs) is a remarkable journey that has transformed the worldof technology over the past several decades. This abstract provides an overview of the comprehensivearticle that explores this evolution. The journey begins with the birth of digital integrated circuits in thelate 1950s and early 1960s when the first ICs containing a small number of transistors emerged. Theseearly ICs laid the groundwork for a technological revolution …
Published in Journal of Microcontroller Engineering and Applications · Vol. 10, Issue 2, 2023 · pp. 15–18 Read article