STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Control & Instrumentation

Design and Verification of Low Power High Speed Voltage Level Shifter Based on Pass Transistor Methodology

  1. Bangaru Usha
  2. G. Susmitha

Abstract

This study explains how a voltage level shifter (LS) can be built using a Wilson current mirror level shifter (WCMLS) with a mirrored output. The proposed fix avoids WCMLS's typical issue of requiring a mirror with a size ratio that is too large. It's a space- and cost-saver. The proposed LS requires less components than its modern versions and uses only tiny components, taking up even less space. The proposed LS has a substantially lower propagation latency and is effective with input voltages close to the threshold. Without the need for any multi-threshold devices, the suggested sub threshold LS may effortlessly convert input voltage levels as low as 50 mV to roughly 1.8 V at the output, as shown by post-layout simulations using a 45GPDK standard CMOS implementation. This research looked at the feasibility of using System Verilog (SV) to verify the AMBA AXI Protocol's incrementing burst feature. The findings are documented.
Support