STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Semiconductor Devices and Circuits

Design and Implementation of Low Power Area Effective 2×4 Decoder for SARM Applications Using 16 nm Technology.

  1. G. Bhavana
  2. A. V. Paramkusam

Abstract

This project involves analysis of Modified Mixed Logic Design abbreviated as MMLD which includes following design logics: Complementary Metal Oxide Semiconductor abbreviated to CMOS logic design, Gate Diffusion Input abbreviated as GDI technique, and Dual Value Logic called as DVL. Two logic styles are used in this paper study to reduce power dissipation and delay time which are fourteen 14-transistor and fifteen 15-transistor decoders. Every situation requires the use of both regular and inverted decoders. In comparison to conventional CMOS logic design, the suggested decoder provides full swing with a smaller number of transistor transistor-counts around 12 transistors. , Which which exhibits a reduced power dissipation and delay when compared to other conventional logic design styles.
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