Dynamic Comparators for Very High-Speed ADC’s

Dr. J. Geetha Ramani; Swapna S.; Priyadharshini .S

Abstract

The need for ultra- low power and space economical analog –to- digital converters (ADCs) is pushing towards the utilization of low voltage CMOS dynamic comparators to maximise the facility potency and speed. the traditional dynamic comparators have options like high input ohmic resistance, no static power dissipation and sensible strength against noise and couple. the downside is that giant numbers of transistors are accustomed minimize the offset, therefore the speed of the comparator is degraded. Double tail comparators overcome the drawbacks in typical comparator by reducing the stacking of transistors with low provide voltage with less delay. However the trans-conductance is low for this comparator. In low power double tail comparator, whilenot complicating the look and by adding few transistors feedback within the regeneration is strong with ends up in reduced delay time. During this paper delay analysis of various dynamic comparators are given with relevance speed and provide voltage. Then supported the delay analysis results, the traditional dynamic comparator is changed in terms of electronic transistor technology and design results as body driven comparator for quick operation even in immoderate low provide voltages. Simulation ends up in 90nm CMOS technology reveals that the delay time is reduced.

Abstract

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