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239 articles for “Thresholding”
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Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications
Abstract: Clock distribution network consumes significant amount of power due to its high switching activity. The high power consumption issue can be satisfactorily addressed by the sub-threshold operation of device, however at the cost of degraded performance and magnified variability. This paper investigates the suitability of conventional clock distribution network for sub-threshold regime and proposes a novel strategy of having an optimized uniform H-tree with a pair of buffer only at …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 22–37 Read article
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A Threshold-Weighted Mathematical Fusion Model for Epidemic Outbreak Prediction Using SEIR Residual Dynamics and Cloud-Based Machine Learning
Abstract: Accurate prediction of epidemic outbreaks is critical for effective public health management, resource planning, early warning generation, and timely intervention by municipal authorities. Traditional compartmental models such as Susceptible–Exposed–Infectious–Recovered (SEIR) offer valuable epidemiological insights and mathematical interpretability; however, they may not adequately capture the complex nonlinear relationships present in real-world urban health systems. Conversely, data-driven machine learning techniques can identify hidden patterns in large datasets but often lack epidemiological structure …
Published in Research & Reviews : Journal of Statistics · Vol. 15, Issue 2, 2026 · pp. 12–19 Read article
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A Two-Dimensional (2D) Analytical Model for Channel Potential and Threshold Voltage of Short Channel Triple Material Gate-Double Halo (TMG-DH) DG MOSFET
Abstract: In the present paper, an analytical model for the channel potential of short channel Triple Material Gate-Double Halo (TMG-DH) DG MOSFET has been presented using parabolic approximation method. Further, the threshold voltage of the device has been calculated using minimum mid channel potential and the result obtained has been compared with the threshold voltage of Triple Material double gate (TMDG) MOSFET in order to show the improvement in the threshold …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 2, 2019 · pp. 13–25 Read article
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Reduction of Ocular Artifacts in Single Channel EEG by EEMD-IMF Thresholding
Abstract: AbstractElectroencephalogram (EEG) is a widely used signal for analyzing the activities of the brain and usually contaminated with artifacts due to the movements of eye, heart, muscles and power line interference. Among these ocular activities creates significant artifacts and makes the analysis difficult. In this paper, ensemble empirical mode decomposition (EEMD) inspired by wavelet thresholding is used for the correction of ocular artifacts (OA) in EEG signals. Unlike the conventional …
Published in Recent Trends in Electronics Communication Systems · Vol. 5, Issue 1, 2018 · pp. 17–25 Read article
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Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device
Abstract: This paper emphasis on the design, fabrication and analysis of 45 nm P type MOSFET device using SILVACO TCAD tool. The analysis was based on variation of various parameters like oxide thickness, threshold implant and halo implant (pockets) to analyze the threshold voltage. The drain versus gate and drain versus gate plots are being plotted using tony-plot. It has been observed that as the thickness of the oxide increases, threshold …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 13–20 Read article
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Implementation of Low Power Shift Registers Using Multi-Threshold CMOS Technique
Abstract: This paper enumerates the design of low power shift registers using dual-edge triggered flip-flop (DETFF). In the conventional shift registers, high leakage current is becoming a significant contributor to power dissipation. In order to overcome this problem, the multi-threshold complementary metal oxide semiconductor (MTCMOS) technology is used for leakage minimization in proposed designs. This technology features both low-threshold and high-threshold voltage MOSFETs. High-threshold voltage MOSFETs reduced the standby leakage current …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 53–61 Read article
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Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device
Abstract: This paper emphasis on the design, fabrication and analysis of 45 nm P type MOSFET device using SILVACO TCAD tool. The analysis was based on variation of various parameters like oxide thickness, threshold implant and halo implant (pockets) to analyze the threshold voltage. The drain versus gate and drain versus gate plots are being plotted using tony-plot. It has been observed that as the thickness of the oxide increases, threshold …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 13–20 Read article
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Wavelets-based Denoising by Optimizing Polynomial Threshold Function
Abstract: In this paper, a wavelets-based technique for denoising of one-dimensional signals is proposed which employs artificial bee colony (ABC) algorithm for optimizing a new polynomial threshold function. The coefficients of the threshold function are optimized dynamically to maximize the output signal to noise ratio (SNR). ABC algorithm calculates the coefficients for maximum output SNR. The proposed technique is tested for three artificial signals, namely blocks, bumps and Doppler signals. Additive …
Published in Current Trends in Signal Processing · Vol. 4, Issue 2, 2014 · pp. 11–23 Read article
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Study of Scaling of MOSFET on Various Electrical Characteristics using Silvaco TCAD Tool
Abstract: MOSFETs are the driving work horse of semiconductor industry. Over the years, the MOSFET device density has been continuously increasing owing to the reduction in channel length of MOSFET device. This article discusses the effect of scaling i.e. channel length and gate oxide thickness on various parameters like threshold voltage, transconductance, maximum drain current and subthreshold slope. It is important to consider that with scaling of the channel length; the …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 11–19 Read article
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Simulation of Threshold Voltage Variation of Enhancement Mode n-channel MOSFET
Abstract: AbstractThe paper focuses on simulation of variation of threshold voltage as a function of effective channel length of the short-channel MOSFETs with a Gaussian-like doping profile. An investigation of short channel effect (SCE) in deep submicron region has been carried out. The validity of the proposed simulation is shown by comparing the results with the numerical calculation and simulation of data obtained by using the commercially available simulation software. Finally, …
Published in Journal of Semiconductor Devices and Circuits · Vol. 4, Issue 2, 2017 · pp. 34–40 Read article
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Performance Analysis of Bootstrapping Techniques to Overcome the Threshold Voltage Drop in NMOS Logic Design
Abstract: Abstract: In this paper, we study the concept of bootstrapping techniques and analyzed its performance in digital CMOS circuits. These bootstrapping circuits are used to increase the gate voltage of transistors so that drain node voltage can be pulled high to overcome the threshold voltage drop problem in NMOS logic design. Also discuss the drawback associated with voltage bootstrapping techniques in NMOS logic design that is sneak path problem between …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 15–20 Read article
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Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating
Abstract: Nowadays design of electronic circuits to meet requirements like high speed, better functionality and low power is a tedious task. Power dissipation in any circuit comprises mainly two components: static power and dynamic power. The dynamic power heavily depends on the switching activity of the circuit. During the transistor switching transitions some spikes may occur, which are called as glitches. These glitches contribute 20–70% of the dynamic power and 20% …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 29–37 Read article
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A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFET’s Threshold Voltage Extractor
Abstract: A CMOS voltage reference circuit featuring MOS transistors threshold voltage extractor has been developed. The circuit implemented using 0.35µm CMOS AMS process generates a reference of 574 mV for a power supply of 3.3V with 726µW power consumption. The circuit presents a variation of 43 ppm/ºC for the –10 to –110ºC temperature, and 18.6 dB PSRR at 1 KHz. A vital analytical approach is presented to provide a universal design …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 14–19 Read article
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Study the Effect of Applied Gate Voltage on Threshold Potential and Carrier Transport Behavior of Three-Terminal Novel Prototype Device having Configuration P-type Si/SiO2/CuFeS2/Al
Abstract: This study presents a trial approach for the fabrication and characterization of a novel p-Si/SiO₂/CuFeS₂/Al field-dependent three-terminal electronic device designed to investigate charge transport behavior across multiple semiconductor junctions under externally applied bias voltages. The proposed prototype incorporates CuFeS₂ (chalcopyrite) as the active semiconductor layer, marking its first reported application in a field-induced electronic device architecture. The device was fabricated using a layered heterostructure consisting of p-type silicon, a silicon …
Published in International Journal of Crystalline Materials · Vol. 3, Issue 2, 2026 · pp. 1–7 Read article
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The Influence of Sediment Deposits in the Threshold Criteria of Sediment Movement in Rigid Boundary
Abstract: An effort is made to develop a simplified methods for the estimation of bed shear stress for rigid boundary for initiation of sediment motion using different bed thickness, bed slopes and different sediment particles diameters (ranging between (0.5mm < d50 < 4.78). The findings were compared with the earlier studies demonstrating that critical shear parameter value for fixed beds is less than the reported values in literature. This come in …
Published in Recent Trends in Civil Engineering & Technology · Vol. 11, Issue 3, 2021 · pp. 31–39 Read article
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Design and Implementation of Low Power and Area Efficient Sub Threshold Level Shifter Using 16 nm CMOS Technology
Abstract: An efficient method of modifying subthreshold voltages is proposed here. As an alternative to static power dissipation, the suggested design allows for charging of internal nodes through VDDH. The force of the pull-down mechanism may be increased by connecting a second auxiliary circuit. The transition energy for input frequencies between 1 and 5 MHz is 84 fJ, the propagation delay is 46 ns, the dynamic power dissipation is 0.3 mW, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 16–24 Read article
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Analysis and Characterization of Circuits for Leakage Power Reduction at Sub-50 nm in CMOS Circuits
Abstract: This paper analyzes various techniques to decrease leakage power in complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) circuits, because due to continuous scaling of CMOS technology there is improvement in speed of semiconductor devices and the side effect of this scaling is leakage power. With the development of technology in CMOS VLSI Circuit, length of transistors has been reduced and speed of operation is increasing simultaneously. As …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 2, 2022 · pp. 11–22 Read article
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Design of Energy Efficient Clock System
Abstract: Energy efficiency is a key metric for energy constrained Ultra Low Power (ULP) VLSI applications such as wireless sensor nodes, pace makers, hearing aids etc. These applications need clock system in their signal processing and communication sub-system. Moreover, clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 1–7 Read article
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A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction
Abstract: Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 3, 2022 · pp. 7–18 Read article
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Analysis of DIBL Effect in MOSFET Working
Abstract: AbstractOne of the most widely used electronic devices, particularly in digital integrated circuits, is the metal insulator semiconductor (MIS) transistor. Most of the existing transistors used in fabrication of integrated chips are with junctions. The device scaling is growing the channel length between junctions in devices are scaling gone down to 10 nm. Drain Induced Barrier Lowering (DIBL) effect is prominent as the feature size of MOS device keep diminishing. …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 33–40 Read article