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59 articles for “Sub threshold”
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Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications
Abstract: Clock distribution network consumes significant amount of power due to its high switching activity. The high power consumption issue can be satisfactorily addressed by the sub-threshold operation of device, however at the cost of degraded performance and magnified variability. This paper investigates the suitability of conventional clock distribution network for sub-threshold regime and proposes a novel strategy of having an optimized uniform H-tree with a pair of buffer only at …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 1, 2019 · pp. 22–37 Read article
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Design and Implementation of Low Power and Area Efficient Sub Threshold Level Shifter Using 16 nm CMOS Technology
Abstract: An efficient method of modifying subthreshold voltages is proposed here. As an alternative to static power dissipation, the suggested design allows for charging of internal nodes through VDDH. The force of the pull-down mechanism may be increased by connecting a second auxiliary circuit. The transition energy for input frequencies between 1 and 5 MHz is 84 fJ, the propagation delay is 46 ns, the dynamic power dissipation is 0.3 mW, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 16–24 Read article
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Design of Energy Efficient Clock System
Abstract: Energy efficiency is a key metric for energy constrained Ultra Low Power (ULP) VLSI applications such as wireless sensor nodes, pace makers, hearing aids etc. These applications need clock system in their signal processing and communication sub-system. Moreover, clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 1–7 Read article
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Study of Scaling of MOSFET on Various Electrical Characteristics using Silvaco TCAD Tool
Abstract: MOSFETs are the driving work horse of semiconductor industry. Over the years, the MOSFET device density has been continuously increasing owing to the reduction in channel length of MOSFET device. This article discusses the effect of scaling i.e. channel length and gate oxide thickness on various parameters like threshold voltage, transconductance, maximum drain current and subthreshold slope. It is important to consider that with scaling of the channel length; the …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 11–19 Read article
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Analysis and Characterization of Circuits for Leakage Power Reduction at Sub-50 nm in CMOS Circuits
Abstract: This paper analyzes various techniques to decrease leakage power in complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) circuits, because due to continuous scaling of CMOS technology there is improvement in speed of semiconductor devices and the side effect of this scaling is leakage power. With the development of technology in CMOS VLSI Circuit, length of transistors has been reduced and speed of operation is increasing simultaneously. As …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 2, 2022 · pp. 11–22 Read article
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A New High Speed Low Power 1 Bit Full Adder
Abstract: This paper proposes a low power, low area and high speed 1-bit full adder compared to earlier 1bit full adder designs. The adder comprises of eight transistors with some modifications over the other existing design, so that it can invariably be used in the device with least nano device dimensions. The proposed design exhibits lower threshold loss and works faithfully in sub-threshold regime with appreciable voltage swing at lower power …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 8–13 Read article
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Modeling and Simulation of Pentacene based Organic Thin Film Transistors with Organic Gate Dielectrics
Abstract: AbstractTwo structures of pentacene organic thin film transistors (OTFT) with organic dielectrics, polymethyl methacrylate (PMMA) and polyvinyl alcohol (PVA) have been numerically simulated with TCAD ATLAS tool. Output and transfer characteristics were simulated and mobility, threshold voltage, sub threshold swing (SS) and current on/off ratio that play a part in the increment of conductivity of device were extracted. The authors show that the semiconductor-insulator interface actively affects the performance of …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 13–18 Read article
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Design and Verification of Low Power High Speed Voltage Level Shifter Based on Pass Transistor Methodology
Abstract: This study explains how a voltage level shifter (LS) can be built using a Wilson current mirror level shifter (WCMLS) with a mirrored output. The proposed fix avoids WCMLS's typical issue of requiring a mirror with a size ratio that is too large. It's a space- and cost-saver. The proposed LS requires less components than its modern versions and uses only tiny components, taking up even less space. The proposed …
Published in Journal of Control & Instrumentation · Vol. 14, Issue 2, 2023 · pp. 30–37 Read article
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Numerical Simulation of Pentacene based Organic Thin Film Transistor with Inorganic Gate Dielectrics
Abstract: This paper presents a 2D numerical simulation and Electrical Characterization of Pentacene (Organic semiconductor) based Organic thin film transistor (OTFT) devices with different inorganic gate dielectrics materials SiO2, Al2O3 and HfO2 and Electrical parameters including; Mobility (µ), Threshold Voltage (Vt), Ion/Ioff ,Sub threshold slope (SS) and Transconductance (gm) are extracted.
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 2, 2019 · pp. 32–38 Read article
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Testing the Efficiency of Background Subtraction Techniques
Abstract: In many video surveillance applications, for instance, detection of abandoned/stolen items or parked vehicles, the detection of desk-sure foreground items is an important task. In this work, we recommend the implementation of a green item detection algorithm that may be employed in actual time embedded devices because of its fast processing. The morphological approach is used for similarly processing to remove noise and to maintain the form of transferring object. …
Published in Current Trends in Information Technology · Vol. 11, Issue 2, 2021 · pp. 29–38 Read article
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Numerical Simulation and Parameter Analysis for Pentacene based Organic thin Film Transistor with HfO2 Gate Dielectric
Abstract: This paper explains 2D numerical simulation and Characterization of Electrical parameter of Pentacene (Organic semiconductor) based Organic thin film transistor (OTFT) devices with HfO2 as a gate dielectric and Electrical parameters including; Threshold Voltage (Vt), Mobility (µ),Ion/Ioff, and Transconductance (gm), Sub threshold slope (SS) are extracted. The numerical simulation includes model for defect density of state and field dependent mobility model.
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 2, 2019 · pp. 28–34 Read article
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Sub-nano Regime DG-MOSFETs
Abstract: AbstractThe significance of device performance of Gallium Nitride based double gate metal-oxide- semiconductor field-effect-transistor has been executed. The simulations were done by Silvaco Atlas simulation software with focusing on non-equilibrium green function (NEGF). Multiple gate length (LG=9.1 nm) was observed to distinguish the transfer characteristics curve. The other concentration was observed for device ON-State Current (ION), OFF-State Current (IOFF), Drain Induced Barrier Lowering (DIBL), Sub Threshold Slope (SS) and Electric …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 3, 2018 · pp. 1–6 Read article
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AUTOMATED PRINTED CIRCUIT BOARD (PCB) DEFECT DETECTION USING DIGITAL IMAGE PROCESSING TECHNIQUE
Abstract: This work presents a Digital Image Processing (DIP) solution involving the use of image filters and processing functions to analyse the reference and the test images of a Printed Circuit Board (PCB) to yield a resulting image in which open and short circuits have been highlighted. The problem solved was the dependence of other PCB defects detection methods on the absence of deformation in the test image and this was …
Published in Journal of Mechatronics and Automation · Vol. 6, Issue 1, 2019 · pp. 1–11 Read article
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On a Nanocomposite Metal Oxide Thin-film Transistor with Nanofilm Gate Dielectric Material: Material Chemistry, Sol–Gel Process and Electronic Worthiness
Abstract: ABSTRACT : ILO based MOTFT is fabricated with PBZ gate dielectric. PBZ is formed over doped Si substrate by cheap sol-gel process. Thin film PBZ is analysed with XRD, UV-Vis and AFM. IZO is used as bottom gate to contact TFT. This device needs only 5V as operating voltage, and so is good for lower electronics <40V. It shows excellent e-mobility 4.5cm2/V/s, with on/off ratio 5x105 and sub-threshold swing 0.35V/decade.
Published in Journal of Thin Films, Coating Science Technology & Application · Vol. 6, Issue 3, 2019 · pp. 8–12 Read article
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A Survey on Recent Approaches for Leakage Power Reduction in MOS Integrated Circuits
Abstract: Today the integrated circuit’s functionalities are increasing day by day with increase in the number of transistors in it. However, the scaling of the transistors, top increase its number, for the same area of an IC reduces its sub-threshold voltage with its increase in the leakage power consumption. Scaling at different scales (45, 60, 90 nm, etc.) leads to major losses, both at static and dynamic phases of the circuits. …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 24–31 Read article
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Reduce the Leakage Current and Power in VLSI Technology
Abstract: Demand for portability Reduce and increase in size, low cost, low dynamic power, low leakage current, low sub threshold current, and the necessity to minimise at least one of these. Circuit complexity increases with circuit integration. Memory and microprocessors are included in mass-produced chips. Microcomputer systems central system memory uses dynamic random-access memory (DRAM). One benefit of DRAM memory is its high speed and capacity integration. The examination of DRAM …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 3, 2023 · pp. 19–25 Read article
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A Survey on Ultra Low Power Design Techniques for IOT Application
Abstract: AbstractInternet of Things (IOT) is evolving as technology’s megatrend, unlocking new opportunities and questions for the semiconductor industry. IOT sensing and actuation devices essentially should be low cost and also should deliver a complete System on Chip (SOC) solution capable of computation, security and wireless communication at very low power levels. The sub-threshold operation, Radio Frequency (RF) redesign, and extreme optimization techniques can minimize power consumption of IOT devices. This …
Published in Current Trends in Information Technology · Vol. 7, Issue 3, 2017 · pp. 9–16 Read article
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A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFET’s Threshold Voltage Extractor
Abstract: A CMOS voltage reference circuit featuring MOS transistors threshold voltage extractor has been developed. The circuit implemented using 0.35µm CMOS AMS process generates a reference of 574 mV for a power supply of 3.3V with 726µW power consumption. The circuit presents a variation of 43 ppm/ºC for the –10 to –110ºC temperature, and 18.6 dB PSRR at 1 KHz. A vital analytical approach is presented to provide a universal design …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 14–19 Read article
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Influence of Dielectric and Active layer Thickness on MgZnO Thin Film Transistor Electrical Characteristics
Abstract: From last decades, Thin Film Transistors Technology uses low-k dielectric material as an insulator. Insulator thickness plays an important role in device dimension. The insulating layer also known as the gate oxide separates the gate electrode from the channel region of the transistor. If the insulating layer is too thin, there is a greater chance that electrons can tunnel through the oxide layer, leading to leakage current. To mitigate this …
Published in Journal of Polymer & Composites · Vol. 11, Issue 5, 2023 · pp. 17–26 Read article
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Advanced Mathematical Modelling of Nanoscale Semiconductor Devices for Low-Power Microelectronic Applications
Abstract: With the ongoing scaling down of semiconductor devices, there is an increasing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. As the sizes of semiconductors continue to decrease, there is a growing need for accurate mathematical models of electrostatic control, carrier transport, leakage current, and power consumption at the nanometer scale. In this work, a common mathematical modelling approach …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 2, 2026 Read article