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24 articles for “Transconductance”
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Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter
Abstract: Basic building block to design an analog circuit is amplifier and it is used for such applications like analog to digital and digital to analog converter, sensor network and many more. Amplifier with lofty gain and high bandwidth will increase the efficiency of design. Present time is talking about development of VLSI technology and everything is related to size of transistor and decreasing power supply in a circuit. Operational transconductance …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 11–15 Read article
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Analysis of Operational Transconductance Amplifier using Low Power Techniques
Abstract: The paper presents a low power design of Current Mirror based Operational Transconductance Amplifier. The analysis of operational transconductance amplifier has been carried out using conventional gate-driven and low power techniques realised with quasi-floating gate, bulk-driven and bulk-driven quasi-floating gate transistors. The comparative analysis of performances of the amplifiers designed using the above techniques indicate that the best performance is achieved by bulk-driven quasi-floating gate approach. Using bulk as input, …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 1, 2015 · pp. 14–22 Read article
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A New Current Mode Quadrature Oscillator using Current Differencing Transconductance Amplifier (CDTA)
Abstract: This paper proposed a new current-mode quadrature oscillator using CDTA (Current Difference Transconductance Amplifier) as the active element. The proposed circuit uses only two grounded or virtually grounded capacitors, two grounded or virtually grounded resistors and two CDTAs. The functionality of the circuit is verified with the PSPICE simulation results.
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 39–42 Read article
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Evaluation of OTA Amplifier Using EEG Signals
Abstract: AbstractOver the last few years, there has been a tremendous exploration in VLSI industries in response to scaling trends towards deep submicron technology. Demand for low power and efficient amplification are rising in day-to-day life. In the process of scaling the CMOS nanometer demand low supply, which is helped to design digital circuit realization at very low power consumption. But it is not valid for analog circuit realization. The related …
Published in Trends in Opto-electro & Optical Communication · Vol. 10, Issue 2, 2020 · pp. 5–14 Read article
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Experimental Investigations to Improve the Electrical Characteristics of Nitride-Based Nanoelectronic High Electron Mobility Transistors
Abstract: In this work, the DC and RF performances of conventional nanoelectronic high electron mobility transistor (HEMT) are compared with those of two individually modified HEMT structures in a nano-scale regime. All simulation results are produced by the SILVACO- ATLAS physical simulator according to the performed designs of HEMT structures. In each of these HEMT structures, the formation of quantum well is demonstrated at unbiased condition. In the DC analysis of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 8, Issue 1, 2021 · pp. 14–30 Read article
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Design and Performance of Semiconductor-Biosensor
Abstract: In this work, a high electron mobility transistor (HEMT) based biosensor is designed to detect the virus-protein. In this work, all the simulation-studies are carried out in the SILVACO-ATLAS physical simulator using the following models: Shockley Read Hall (SRH), band gap narrowing, Auger recombination, and Fermi Dirac statistics. Newton trap numerical solver is used in the device simulation. Conduction band engineering of the biosensor is studied. DC and RF properties …
Published in Journal of Semiconductor Devices and Circuits · Vol. 8, Issue 2, 2021 · pp. 1–13 Read article
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Optimization and Analysis of InGaAs Vertical Nanowire Transistor for Memory Array Applications
Abstract: In this paper, we present a cylindrical gate all around In 0.53 Ga 0.47 As Vertical Nanowire Transistor (VNWT) on silicon at ultra-shortchannel gate length 14nm by numerical simulation approach. The In 0.53 Ga 0.47 As VNWT device dimensions like diameter, source and drainextension length and channel doping are taken as critical process parameters and optimized for better performance. The proposed device isscalable up-to 10nm with a maximum On-current of …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 32–44 Read article
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Study of Scaling of MOSFET on Various Electrical Characteristics using Silvaco TCAD Tool
Abstract: MOSFETs are the driving work horse of semiconductor industry. Over the years, the MOSFET device density has been continuously increasing owing to the reduction in channel length of MOSFET device. This article discusses the effect of scaling i.e. channel length and gate oxide thickness on various parameters like threshold voltage, transconductance, maximum drain current and subthreshold slope. It is important to consider that with scaling of the channel length; the …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 11–19 Read article
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Improvements in Analog Performance of Dual Metal Gate based Silicon-on-Insulator Junctionless Transistor with Pocket Doped Window
Abstract: This paper elucidates the impact of the pocket doped window on the analog performance of dual metal gate based silicon-on-insulator junctionless transistor (DMG SOIJLT). The analog parameters of the proposed SOIJLT are compared with DMG based conventional SOIJLT. The findings of analog performance comparison reveal that transconductance (gm), transconductance generation factor (TGF), output conductance (gd), output resistance (r0), intrinsic gain (AV), and cut-off frequency (fT) have improved for DMG PD-SOIJLT …
Published in Journal of Microelectronics and Solid State Devices Read article
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Influence of Graded Channel on Performance of Symmetric Double Material Gate Insulator FDSOI MOSFET
Abstract: Abstract: In this paper, we investigate the effect on the linearity, analog and RF performance of graded channel in case of hetero-gate-dielectric FDSOI MOSFET with higher doping at source end and low doping at drain end. The major figure of merits (FOMs) studied are on-state drive current (ION), transconductance (gm), total gate capacitance (Cgg), cut-off frequency (fT), higher order derivative of transconductance (gm’, gm’’), intermodulation distortion (IMD3) and third- order …
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 1, 2019 · pp. 12–17 Read article
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Improvements in Analog Performance of Dual Metal Gate based Silicon-on-Insulator Junctionless Transistor with Pocket Doped Window
Abstract: This paper elucidates the impact of pocket doped window on the analog performance of dual metal gate based silicon-on-insulator junctionless transistor (DMG SOIJLT). The analog parameters of proposed SOIJLT is compared with DMG based conventional SOIJLT. The findings of analog performance comparison reveal that transconductance (gm), transconductance generation factor (TGF), output conductance (gd), output resistance (r0), intrinsic gain (AV), and cut-off frequency (fT) have improved for DMG PD-SOIJLT as compared …
Published in Journal of Microelectronics and Solid State Devices · Vol. 8, Issue 1, 2021 · pp. 1–8 Read article
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Impact of Source/Drain Engineering on Performance of Single Gate and Dual Gate Junctionless MOSFET
Abstract: Abstract: This letter is the study on impact of source/drain engineering on Single Gate (SG) and Dual Gate (DG) Junctionless MOSFET. Both the proposed MOSFET have Gate Stacking and highly doped source/drain region, so name suggested is Highly Doped Source Drain Gate Stack Junctionless (HDSD-GSJL) MOSFET. Here we investigate the effect of highly doped source/drain, gate stacking and double gate on junctionless MOSFET. The investigation is performed in relations of …
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 1, 2019 · pp. 10–14 Read article
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A Comprehensive Review of CMOS Analog Circuit Design Techniques for Low-Power VLSI Systems
Abstract: CMOS analog circuit design plays a significant role in the development of modern low-power Very Large-Scale Integration (VLSI) systems used in wireless communication, biomedical devices, portable electronics, embedded systems, and Internet of Things (IoT) applications. Research on low-power CMOS analogue design methodologies has intensified because to the growing need for high-performance, small, and energy-efficient electronic products. However, reducing power consumption while maintaining signal accuracy, noise performance, stability, bandwidth, and overall …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Comparative Analysis of FD-DMDG SON MOSFET over FD DMDG SOI MOSFET
Abstract: AbstractIn the recent past, Silicon-on-Insulator (SOI) shows better device performance in comparison to bulk Silicon devices but it still suffers from different short channel effects (SCEs). Recently a structure, Silicon on Nothing (SON), has been suggested and investigated. It is structured to be capable of substantial reduction of SCEs and present better electrical characteristics in comparison to SOI. The absence of the buried layer results in the reduced electrostatic coupling …
Published in Journal of Electronic Design Technology · Vol. 9, Issue 1, 2018 · pp. 9–16 Read article
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Numerical Simulation and Modeling of Graphene Field Effect Transistors for High Frequency Applications
Abstract: AbstractIn this paper numerical simulation of graphene field effect transistor (GFET) has been performed using finite element method by solving Poisson's equation, continuity equation and energy balance equation self consistently. Various performance characteristics including charge distribution, band gap energy, transfer and output characteristics, electrostatic potential distribution and transconductance have been extracted.Keywords: Graphene field effect transistor (GFET), energy balance equation, mobility, ambipolar, numerical simulationCite this ArticleAshish Jha, Dwivedi ADD. Numerical Simulation …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 27–33 Read article
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Numerical Simulation of Pentacene based Organic Thin Film Transistor with Inorganic Gate Dielectrics
Abstract: This paper presents a 2D numerical simulation and Electrical Characterization of Pentacene (Organic semiconductor) based Organic thin film transistor (OTFT) devices with different inorganic gate dielectrics materials SiO2, Al2O3 and HfO2 and Electrical parameters including; Mobility (µ), Threshold Voltage (Vt), Ion/Ioff ,Sub threshold slope (SS) and Transconductance (gm) are extracted.
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 2, 2019 · pp. 32–38 Read article
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SPICE Modeling of LDMOSFET Transistor
Abstract: AbstractHigh voltage integrated circuits, these days are the most viable alternatives to discrete circuits for various applications. The popular amongst them is the lateral double diffused MOS transistor (LDMOS). It is based on the lightly doped drain (LDD) concept. The constraint that occurred in modeling LDMOS is to minimize the on-resistance along with maintaining a high breakdown voltage. To achieve the objective, the help of RESURF (Reduced Surface Field) concept …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 1, 2016 · pp. 42–57 Read article
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Numerical Simulation and Parameter Analysis for Pentacene based Organic thin Film Transistor with HfO2 Gate Dielectric
Abstract: This paper explains 2D numerical simulation and Characterization of Electrical parameter of Pentacene (Organic semiconductor) based Organic thin film transistor (OTFT) devices with HfO2 as a gate dielectric and Electrical parameters including; Threshold Voltage (Vt), Mobility (µ),Ion/Ioff, and Transconductance (gm), Sub threshold slope (SS) are extracted. The numerical simulation includes model for defect density of state and field dependent mobility model.
Published in Journal of Semiconductor Devices and Circuits · Vol. 6, Issue 2, 2019 · pp. 28–34 Read article
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3D Simulation of Multi-Gate Mosfet Analysis for Analog Circuit Design Parameters
Abstract: Chip density and performance improvements of semiconductor devices have been driven by their aggressive scaling. The performance of multi-gate FET for analog applications is explored in this paper. Analog operation of CMOS devices and its parameters are very important for future cutting edge technologies. The multi-gate technology shows excellent scalability and better immunity to short channel effects in MOSFETs. They are being easily assessed for CMOS applications beyond the 45 …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 2, 2014 · pp. 1–8 Read article
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DC and RF Analysis on Specific Quantum-Well Heterostructures
Abstract: Polarization-graded AlGaN back-barrier nano-layer is introduced in high electron mobility transistor (HEMT) structure to have an improved drain current characteristics and better radio-frequency performance, using two-dimensional drift-diffusion simulation by SILVACO-ATLAS physical simulator. In this work, the AlGaN/AlN/GaN/AlGaN/GaN double heterojunction HEMT structure is optimised with graded back barrier layer to study the DC and RF performances. Investigation of this structure with graded back barrier layer is the novelty of this work. …
Published in Journal of Semiconductor Devices and Circuits · Vol. 9, Issue 1, 2022 · pp. 1–13 Read article