STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of VLSI Design Tools and Technology

Optimization and Analysis of InGaAs Vertical Nanowire Transistor for Memory Array Applications

  1. Subha Subramaniam

Abstract

In this paper, we present a cylindrical gate all around In 0.53 Ga 0.47 As Vertical Nanowire Transistor (VNWT) on silicon at ultra-shortchannel gate length 14nm by numerical simulation approach. The In 0.53 Ga 0.47 As VNWT device dimensions like diameter, source and drainextension length and channel doping are taken as critical process parameters and optimized for better performance. The proposed device isscalable up-to 10nm with a maximum On-current of 5.6mA, leakage current of 2nA and I on /I off ratio up to 10 6 . The ac characteristics of theproposed In 0.53 Ga 0.47 As VNWT is analyzed for various gate voltages and gate to source capacitance, gate to drain capacitance andtransconductance are obtained. The device can operate at a cut off frequency of 6 GHz and a maximum operating frequency up to 9.8GHz. A 3x1,5x1 cross bar memory layout arrangement and a 3x3 memory array are built using In 0.53 Ga 0.47 As VNWT devices. In 5x1 array arrangement InGaAsVNWT shows 44% better I on /I disturb ratio than horizontal HNWT devices. The VNWT device can be used as a memory element in high frequency,low power applications.

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