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71 articles for “Gate voltage”
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Numerical Simulation of Pentacene based Organic Thin Film Transistor with Inorganic Gate Dielectrics
Abstract: This paper presents a 2D numerical simulation and Electrical Characterization of Pentacene (Organic semiconductor) based Organic thin film transistor (OTFT) devices with different inorganic gate dielectrics materials SiO2, Al2O3 and HfO2 and Electrical parameters including; Mobility (µ), Threshold Voltage (Vt), Ion/Ioff ,Sub threshold slope (SS) and Transconductance (gm) are extracted.
Published in Journal of Microelectronics and Solid State Devices · Vol. 6, Issue 2, 2019 · pp. 32–38 Read article
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A Comparative Study on Carbon Nanotube MOSFET, Silicon Nanowire MOSFET and Single Gate MOSFET
Abstract: Among many of the concerns for the researchers in nano-electronics, Single Gate MOSFET, Silicon Nanowire MOSFET and Carbon Nanotube MOSFET were very popular three. All of them are different in their structures and performance. This paper is focused on the comparison of their characteristics in terms of Current- voltage relations, Mobility charge density and Quantum capacitance. ‘FETToy’ in ‘nanohub’ was used to simulate the predefined models in room temperature. Drain …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 2, 2015 · pp. 7–12 Read article
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Stochastic Differential Equation Noise Analysis of Common-Gate Amplifier with Capacitive Load
Abstract: In this paper, common-gate amplifier with capacitive load is analysed to observe the effect of noise on the circuit. We used stochastic differential equations to analyse the effect of extrinsic noise. We adopted time domain approach and used SDE to obtain autocorrelation function for the output voltage. We determined mean and variance of the output noise. This analysis leads to obtain the circuit with better noise performance. Keywords: Common-gate amplifier, …
Published in Journal of Semiconductor Devices and Circuits · Vol. 5, Issue 1, 2018 · pp. 1–4 Read article
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DFT Compatible Low Power EDAC Based on Clock Gating
Abstract: The in-situ EDAC architecture is normally hired in timing-error tolerant circuits in a try and decrease the conservative timing protect band due to procedure, voltage, and temperature (PVT) fluctuations. But with the addition of the latch-based totally data channel, extra detection, and propagation common sense, it makes the implementation of the layout for- testability (DFT) tough. We present a new low area test overhead DFT EDAC architecture with extreme reduction …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 1, 2025 · pp. 41–53 Read article
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Machine Learning Assisted Optimization of Nanoscale MOSFET Parameters Using TCAD Simulation
Abstract: This paper presents a machine learning (ML) assisted framework for the multi-objective optimization of nanoscale bulk n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) with a 10 nm physical gate length, high-k HfO₂ gate dielectric, and TiN metal gate. Technology computer-aided design (TCAD) simulations employing drift-diffusion transport, Shockley-Read-Hall recombination, Lombardi mobility degradation, and density- gradient quantum correction models are used to generate a parametric dataset of 2,400 device configurations spanning gate length (L), …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 10–19 Read article
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Simulation Study of Process Variations in Double Gate Junctionless Field-Effect Transistors
Abstract: This work discusses the process variations in symmetrical double-gate (DG) junctionless (JL) field-effect transistors (FETs) by device simulation. Output I-V characteristics along with subthreshold slope increase, DIBL variations with drain voltage and threshold voltage shift variations are systematically analyzed with the general variability issues including oxide thickness, channel thickness and doping concentration. Potential distribution in the body channel region is also analyzed. Optimum values of the variability factors are considered …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 2, 2015 · pp. 18–27 Read article
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Investigation and Dependency Analysis of Silicon Film Thickness on Performance of Surrounding Gate MOSFET at Subthreshold Regime
Abstract: The characteristics of cylindrical gate all around MOSFET have been studied in terms of the dependence of various device performance metrics on silicon film thickness (Tsi). In this work, the effect of silicon film thickness on numerous performance metrics like threshold voltage (Vt), On current (Ion), subthreshold leakage current (Ioff), On-Off current ratio (Ion/Ioff) and DIBL of cylindrical GAA are comprehensively evaluated and analysed. It has been observed that cylindrical …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 2, 2018 · pp. 49–54 Read article
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Modeling and Simulation of Pentacene based Organic Thin Film Transistors with Organic Gate Dielectrics
Abstract: AbstractTwo structures of pentacene organic thin film transistors (OTFT) with organic dielectrics, polymethyl methacrylate (PMMA) and polyvinyl alcohol (PVA) have been numerically simulated with TCAD ATLAS tool. Output and transfer characteristics were simulated and mobility, threshold voltage, sub threshold swing (SS) and current on/off ratio that play a part in the increment of conductivity of device were extracted. The authors show that the semiconductor-insulator interface actively affects the performance of …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 13–18 Read article
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Performance Evaluation of Single Phase Cascaded Nine Level Inverter using Photovoltaic (PV) SystemPerformance Evaluation of Single Phase Cascaded Nine Level Inverter using Photovoltaic (PV) System
Abstract: Multilevel inverters are considered at present as the state of the art power conversion systems for high power and power quality demanding applications. This paper’s objective is to propose a modified cascaded nine-level inverter topology for a virtually sinusoidal output voltage, less number of power switches, results in decreased complexity and reduced total harmonic distortion (THD). The structure is simple and easy to be extended to higher level but also …
Published in Trends in Electrical Engineering · Vol. 8, Issue 1, 2018 · pp. 30–47 Read article
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Technometric Portrait of Sri Vinod Dham, an Indo-US Engineer, Father of Intel Pentium Process: A Quantitative Analysis
Abstract: Vinod Dham is recognized as the ‘Father of Pentium Chip’ or ‘Father of Intel Pentium Process’ in the field of the computer industry, and as an Indo-American pioneer from Silicon Valley. He has contributed 10 research papers during 1982–1986, with an average of two papers per year. This study tries to analyze his contributions through a bibliometric study and draw his familiarity as a world-famous electronic technologist. Data has been …
Published in Research & Reviews : Journal of Statistics · Vol. 14, Issue 3, 2025 · pp. 16–25 Read article
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Polypyrrole-Based Conductive Polymer-Gated Single Electron Transistor with Deep Neural Network Assistance for Biomedical Energy Harvesting and Charge Detection
Abstract: The increasing demand for intelligent biomedical monitoring systems has accelerated research into ultra-low-power sensing technologies capable of operating with high sensitivity and minimal energy consumption. Conductive polymers have attracted considerable attention for biomedical and nanoelectronic applications due to their tunable electrical properties, biocompatibility, and environmental stability. Among them, Polypyrrole (PPy) is a promising functional polymer that can enhance charge transport and electrostatic coupling in nanoscale devices. In this work, a …
Published in Journal of Polymer & Composites · Vol. 14, Issue 4, 2026 Read article
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Closed Loop Control of Multi Level Inverter Tied with 415 V AC Source Using SV-PWM for Renewable Energy
Abstract: In this work, 415 V AC source is interfaced with three-level diode clamped inverter in which renewable energy source is used as a DC source, solar energy is used which is most popular renewable energy source. The obtained DC from the solar irradiation is fed to MPPT (Maximum Power Point Tracking) to utilize voltage at maximum power (DC). The perturb and observe technique is used in this work to track …
Published in Journal of Power Electronics and Power Systems · Vol. 6, Issue 1, 2016 · pp. 55–65 Read article
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Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops
Abstract: This paper presents phase frequency detector using different gates like AND, NOR and NAND and comparative simulation result analysis is carried out. The simulation is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. NAND based PFD has lowest power consumption then other and it is 4.2587 µW at 1 GHz Frequency and dead zone to 18 ps which means having approximately zero dead zone problem. …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 18–28 Read article
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Automatic Switch cum Fuse IC for Low Voltage, Low Power, High Performance Current Conveyors
Abstract: The paper focuses on the analysis of switch cum fuse IC in signal processing. In signal processing it is proposedto prevent the damage of main IC from the external electrical fluctuations which are common in -these days. Theproposed FUSE IC is also able to act as fuse for many times for main IC so that it can prevent the damage. It’slike the work of MCB but a step ahead that …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 21–25 Read article
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R-M and M-R Model for Interpreting Logic State of Memristor Aided NOR with Enhanced Noise Margin
Abstract: Memristive crossbar arrays are one of the fascinating subjects in the field of nanoelectronics and memory devices. The arrangement of arrays consists of grid-like structure with rows and columns of memristors which are resistive devices that can preserve their resistance state even after power is turned OFF. They have now emerged as a promising alternative to traditional memory technologies due to their high density, non-volatility and low power consumption. This …
Published in Recent Trends in Mathematics · Vol. 1, Issue 1, 2024 · pp. 35–41 Read article
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Improvement of Design Issues in FinFET based Design Techniques for XOR and XNOR Circuits at 45 nm Technology
Abstract: The scaling of conventional CMOS circuit inclines to the short channel effect due to leakage current increase in the circuit. To minimize the short channel effect, FINFET can be used in place of conventional CMOS circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. This paper assesses and compares the performance of XOR and XNOR logic circuits. This …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 22–35 Read article
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A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction
Abstract: Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 3, 2022 · pp. 7–18 Read article
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A Review on High Electron Mobility Transistors
Abstract: AbstractThe demand for high speed semiconductor devices is increasing in recent years with the rapid development of the high frequency wireless and fiber optical communication systems. High electron mobility transistor (HEMT) is an important device and an excellent candidate for millimeter, sub-millimeter and microwave applications. Also, these devices have high frequency, high speed, low noise, high breakdown voltage, low cost and other power handling capabilities. Due to these reasons, they …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 2, 2016 · pp. 1–10 Read article
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Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology
Abstract: The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 28–34 Read article
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Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology
Abstract: The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 28–34 Read article