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36 articles for “digital arithmetic”
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute-intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered by …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 2, 2022 · pp. 22–33 Read article
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A Novel Binary Arithmetic Computational Method
Abstract: The proposed algorithm for arithmetic operations presents an innovative and intriguing approach, primarily centered around the use of counters and the manipulation of '1's in binary representations. This algorithm promises to introduce significant advancements in computational efficiency and accuracy, making it a potential game-changer in the field of arithmetic calculations. At the core of this method lies the reliance on the number of '1's in each location within a binary …
Published in Research & Reviews: Discrete Mathematical Structures · Vol. 10, Issue 1, 2023 · pp. 21–25 Read article
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Design and Implementation of A 4-bit Multiplier using Wallace Tree Architecture in 180 nm Technology
Abstract: Over the period of last decade, power dissipation has become one of the most important factors for VLSI designers in the design of most digital systems. Even though the speed and area are considered to be the critical factors in design of digital systems, there is a trade of with power consumption. Adders and multipliers are the most important arithmetic units in a processor and the major sources of power …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 1, 2015 · pp. 17–23 Read article
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Area and Speed Efficient Floating Arithmetic Logic Unit Implementation on Hybrid FPGAS
Abstract: Proposed design of an Area and Speed optimized field arithmetic logic unit (FALU) for modern computing of advanced processors, as we are aware that in most of the DSP (Digital Signal Processors) FALU is a critical component for continuous calculation of signs and ongoing information to meet the constant situation of sign handling it is exceptionally needed to make calculation quicker as could be expected so we have thought of …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 3, 2021 · pp. 29–34 Read article
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Simulation of Adder Circuit Using Reversible Gates in Verilog HDL
Abstract: The emerging field of quantum computing uses quantum logic gates. The reversibility of logic gates is an important aspect of quantum logic gates used in VLSI and quantum computing. Reversibility ensures that power consumption is minimized. This study explores the field of reversible logic and utilizes Peres gate to develop a full adder circuit that shows a significant reduction in power consumption in simulations performed in Xilinx Vivado. We have …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 32–38 Read article
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Half Adder Using Different Design Styles: A Review on Comparative Study
Abstract: AbstractA half adder is a digital logic circuit that performs addition of two single bit binary numbers. Generally, in various types of processors, adders are used to perform arithmetic and logical operations .In this paper, working of half adder is analysed by designing it by using three different logic styles, i.e., CMOS logic, Transmission Gate Logic (TGL) and Pass Transistor Logic (PTL). The comparison has been made between the circuits …
Published in Journal of Advancements in Robotics · Vol. 7, Issue 3, 2020 · pp. 26–32 Read article
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Building Knowledge with a Hands-on 8-bit CPU Architecture Simulation Kit for Students
Abstract: It is now crucial for students studying electronics and information technology to comprehend computer architecture and logic design. Hands-on, practical instruction is required to assist students in understanding Computer Organization and Architecture (COA). Our kit, which covers essential components including bus interfaces, arithmetic, and logic units (ALU), memory structures, and functional registers, is based on the Von Neumann architecture. Theoretical techniques like block diagrams and top level diagrams are typically …
Published in Journal of Electronic Design Technology · Vol. 15, Issue 3, 2024 · pp. 1–9 Read article
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A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture
Abstract: A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 37–46 Read article
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Smart Contract: A New Buzz Word for Reliable Decentralized Network
Abstract: Blockchain technology has emerged as a foundational distributed-ledger architecture enabling decentralized, transparent, and tamper-resistant data management across diverse digital ecosystems. This paper presents an integrated review of blockchain fundamentals, consensus mechanisms, smart contract design, and real-world applications beyond cryptocurrencies. It discusses the evolution of smart contracts as automated, self-executing programs that remove intermediaries and ensure deterministic execution, while highlighting critical security vulnerabilities such as reentrancy, arithmetic overflows, and improper access …
Published in Journal of Open Source Developments · Vol. 13, Issue 1, 2026 · pp. 35–41 Read article
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Improvement of Design Issues in FinFET based Design Techniques for XOR and XNOR Circuits at 45 nm Technology
Abstract: The scaling of conventional CMOS circuit inclines to the short channel effect due to leakage current increase in the circuit. To minimize the short channel effect, FINFET can be used in place of conventional CMOS circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. This paper assesses and compares the performance of XOR and XNOR logic circuits. This …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 22–35 Read article
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Optimized Hardware Realization of AES for High-Throughput FPGA Platforms
Abstract: The Advanced Encryption Standard (AES) is the predominant symmetric-key cryptographic algorithm used for securing digital communication across embedded systems, IoT devices, cloud infrastructures, and defense networks. Although software-based AES implementations offer flexibility, they often fail to meet the high-speed, low-latency, and energy-efficient requirements of modern real-time applications. Reconfigurable hardware platforms such as Field-Programmable Gate Arrays (FPGAs) provide a powerful alternative by enabling architectural customization, intrinsic parallelism, and optimized hardware acceleration. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 3, Issue 2, 2025 · pp. 11–22 Read article
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Exploring the Studies of Mathematics: Foundations, Evolution, Pedagogy and Prospects
Abstract: Mathematics, often regarded as the universal language of science and logic, has evolved through centuries as both a tool for understanding the natural world and a discipline of abstract reasoning. This study explores the multifaceted dimensions of mathematics by examining its foundations, historical evolution, pedagogical approaches, and future prospects. The foundational aspects trace back to ancient civilizations—Babylonian arithmetic, Greek geometry, and Indian and Arabic contributions to algebra— highlighting how early …
Published in Recent Trends in Mathematics · Vol. 2, Issue 2, 2025 · pp. 25–31 Read article
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The Evolution and Impact of Numbers: From Ancient Tallies to Quantum Computing: Review Article on Numbers
Abstract: Numbers are among the most fundamental constructs in human civilization, serving as the backbone of mathematics, science, technology, and virtually every aspect of daily life. They represent not only quantities and measures but also relationships, structures, and patterns that underpin the fabric of human understanding. From the earliest tallies etched on bones by prehistoric humans to the sophisticated numerical systems embedded in today’s artificial intelligence and quantum computing, the evolution …
Published in Research & Reviews: Discrete Mathematical Structures · Vol. 12, Issue 3, 2025 · pp. 15–19 Read article
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Low Power 8-Bit Square Root Carry Select Adder Constructed By Using 8 Transistor Full Adder
Abstract: Carry select adder is the high speed adder which is designed to speed up arithmetic operations and to reduce the computation time. Carry select adder is used to perform fast arithmetic functions in data processing processors. Low power consumption, reduced area, reduced delay and increased speed are the most important features of the modern electronic system design. In this proposed work, 8 transistor full adder (8T full adder) is used …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 25–29 Read article
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Algebraic Foundations of AES (Advanced Encryption Standard): Group Theory and Finite Field Applications in Symmetric Cryptography
Abstract: This paper presents a mathematical study of symmetric cryptographic algorithms, with a particular emphasis on the Advanced Encryption Standard (AES), which is one of the most widely used encryption schemes in modern security applications. The study highlights how abstract mathematical frameworks such as group theory, finite fields, and vector space concepts provide the foundation for the design, implementation, and analysis of AES. By approaching the algorithm from a mathematical perspective, …
Published in Recent Trends in Mathematics · Vol. 2, Issue 1, 2025 · pp. 12–16 Read article