Area and Speed Efficient Floating Arithmetic Logic Unit Implementation on Hybrid FPGAS

Sateesh Kourav; Sunil Shah

doi:10.37591/rrjoesa.v9i3.874

Abstract

Proposed design of an Area and Speed optimized field arithmetic logic unit (FALU) for modern computing of advanced processors, as we are aware that in most of the DSP (Digital Signal Processors) FALU is a critical component for continuous calculation of signs and ongoing information to meet the constant situation of sign handling it is exceptionally needed to make calculation quicker as could be expected so we have thought of thought to configuration quick FALU. The chip region is one more necessary to plan a smaller module and less power. A FALU module has three sub-modules FM, FA and WB, advancing these we can enhance by and large plan we have gone through different methodologies for Floating augmentation and drifting expansion we intend to involve Mitchell calculation for duplication and Wallace for expansion and we will utilize coarse grain of Vertex-2 for generally coherent activities. We have a proposition to blend Mitchell and Wallace procedures for planning FM and FA submodules and to configuration top module of plan pecking order including coarse-grain rationale modules WB's alongside FA and FM. Their top module is a 16-digit FALU module.

Abstract

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