6 publications
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The Design and Analysis of a High Bandwidth Patch Antenna Loaded with Double-L shaped Parasitic and Super-Strate ComponentsBy Sateesh Kourav, Kirti Verma, Jagdeesh Kumar Ahirwar, Sunil Kumar Shah, Mukul Jangid, Yashwant Singh Thakur
Abstract: A patch antenna having parasitic components in the shape of a double-L. It is shown how to make a directional slot antenna using a parasitic patch and a windowed superstrate. The recommended antenna may readily obtain high-gain properties due to its composition. The suggested antenna's impedance bandwidth has been measured. Internet of Things (IoT) apps to make their data more accessible, wireless communication technology integration is required. This work proposes …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 10, Issue 2, 2023 · pp. 1–13 Read article →
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Study And Literature Analysis of The Coarse-Grained Logic Interface with Floating-Point Arithmetic UnitBy Devendra Singh Thakur, Sateesh Kourav, Prof. Sunil Kumar Shah, Yashwant Singh Thakur
Abstract: Field-Programmable Gate Arrays (FPGAs) have become an essential digital circuit implementation techni que. The research looks at the design parameters by evaluating the building of an arithmetic logic unit (ALU) in Xilinx Vivado utilizing Hardware Description Language (HDL) and implementing common Field Programmable gate arrays (FPGAs). The ALU is a logic design component in digital computers that seeks to deliver optimal algorithms to maximize the usage of available hardware. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 45–55 Read article →
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Coarse-grained Logic Interface with Floating-point Arithmetic Unit: A ReviewBy Devendra Singh Thakur, Sunil Kumar Shah, Sateesh Kourav, Anoop Kumar Dubey, Yashwant Singh
Abstract: One of the key elements of their design, which has a substantial impact, is their choice of programmable connectivity and logic capabilities. The FPGA architecture has a significant impact on the speed performance, space efficiency, and power consumption of the finished device. This examination examines the evolution of programmable logic devices over time, the underlying programming paradigms that underpin programmability, and the most important findings from architectural system research. We …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 11, Issue 2, 2023 · pp. 18–24 Read article →
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A Circuit Approach for CMOS VLSI Circuit Leakage Power ReductionBy Prajyant Pathak, Sateesh Kourav
Abstract: Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 3, 2022 · pp. 7–18 Read article →
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Area and Speed Efficient Floating Arithmetic Logic Unit Implementation on Hybrid FPGASBy Sateesh Kourav, Sunil Shah
Abstract: Proposed design of an Area and Speed optimized field arithmetic logic unit (FALU) for modern computing of advanced processors, as we are aware that in most of the DSP (Digital Signal Processors) FALU is a critical component for continuous calculation of signs and ongoing information to meet the constant situation of sign handling it is exceptionally needed to make calculation quicker as could be expected so we have thought of …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 3, 2021 · pp. 29–34 Read article →
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Analysis of High Performance 6-Stage 64-Bit MIPS RISC Pipelined Processor Using FPGA VHDLBy Sateesh Kourav, Sunil Shah
Abstract: The powerful 6-stage 64-bit MIPS RISC processor improves the speed and importance of the pipeline process. This is done for 64 steps, six steps in high detail, better for high speed and advanced technology. In a comparative study, our proposed architecture has reduced and increased power by 12% speed compared to our nearest counterpart. Simulation result Xilinx are done with proven the superiority of the platform and our model. Pipelining …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 2, 2021 · pp. 14–19 Read article →