Analysis of High Performance 6-Stage 64-Bit MIPS RISC Pipelined Processor Using FPGA VHDL

Sateesh Kourav; Sunil Shah

doi:10.37591/rrjoesa.v9i2.848

Abstract

The powerful 6-stage 64-bit MIPS RISC processor improves the speed and importance of the pipeline process. This is done for 64 steps, six steps in high detail, better for high speed and advanced technology. In a comparative study, our proposed architecture has reduced and increased power by 12% speed compared to our nearest counterpart. Simulation result Xilinx are done with proven the superiority of the platform and our model. Pipelining is a technique that exploits parallelism, to achieve increased throughput between instructions in a sequential instruction stream, and that reduces the total time to complete a job. The main objective of this architecture is to create a low-power highperformance structure that meets all the design requirements. Important factors like power, frequency, area, propagation delay are analyzed using Xilinx tools. The basic functional blocks of a processor include input/output blocks, configurable logic blocks, block RAM, and a digital clock manager, and each block allows multiple sources to be connected for routing. Auxiliary units increase the performance of the processor. The comparative study nullifies the designed model in terms of area, power and frequency.

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