2 publications
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Published Subscription
Area and Speed Efficient Floating Arithmetic Logic Unit Implementation on Hybrid FPGASBy Sateesh Kourav, Sunil Shah
Abstract: Proposed design of an Area and Speed optimized field arithmetic logic unit (FALU) for modern computing of advanced processors, as we are aware that in most of the DSP (Digital Signal Processors) FALU is a critical component for continuous calculation of signs and ongoing information to meet the constant situation of sign handling it is exceptionally needed to make calculation quicker as could be expected so we have thought of …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 3, 2021 · pp. 29–34 Read article →
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Published Subscription
Analysis of High Performance 6-Stage 64-Bit MIPS RISC Pipelined Processor Using FPGA VHDLBy Sateesh Kourav, Sunil Shah
Abstract: The powerful 6-stage 64-bit MIPS RISC processor improves the speed and importance of the pipeline process. This is done for 64 steps, six steps in high detail, better for high speed and advanced technology. In a comparative study, our proposed architecture has reduced and increased power by 12% speed compared to our nearest counterpart. Simulation result Xilinx are done with proven the superiority of the platform and our model. Pipelining …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 2, 2021 · pp. 14–19 Read article →