STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Microcontroller Engineering and Applications

Design and Implementation of A 4-bit Multiplier using Wallace Tree Architecture in 180 nm Technology

  1. Shrishail Pattanashetti
  2. R. B. Shettar

Abstract

Over the period of last decade, power dissipation has become one of the most important factors for VLSI designers in the design of most digital systems. Even though the speed and area are considered to be the critical factors in design of digital systems, there is a trade of with power consumption. Adders and multipliers are the most important arithmetic units in a processor and the major sources of power dissipation. Various architecture styles can be used to implement these modules, each one of it having their own limitations. The objective of project is to investigate the power and delay performances of adder circuits in different CMOS logic styles, which will be used in different design stages of the multiplier. Circuits are designed in Cadence EDA tool and simulated using Spectre Virtuoso tool with 0.18 um technology. Comparing results of the adder circuits in different CMOS logic styles show that hybrid CMOS adder circuits are faster and dissipate less power. Different binary adders such as ripple carry adder and carry propagate adder are designed using hybrid CMOS logic. It is designed using Wallace tree architecture. Ripple carry adder and carry propagate adders are used as a part of final adder along with other adders in the design of multiplier. Simulation results show that multiplier with carry propagate adder as a final adder gives 70% faster response compared to multiplier with ripple carry adder as a final adder.

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