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190 articles for “VLS”
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An Explicit Approach to Compare Crosstalk Noise and Delay in VLSI RLC Interconnect Modeled with Skin Effect with Step and Ramp Input
Abstract: As the technology is acquiring frequency of the Giga-hertz range noise and delay calculations andavoidance of such factors in VLSI interconnects have become dominant to be considered. This paperrepresents a comparison between the crosstalk noise voltage level measured when the RLC on-chipinterconnect was modeled when the skin effect was considered under step input and the crosstalk voltagemeasured when the RLC line was modeled with skin effect under ramp input. In …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 1–8 Read article
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A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure
Abstract: Floor planning is a key issue in VLSI physical plan. The floor planning issue can be defined as that a given arrangement of 3D rectangular pieces while limiting reasonable cost capacities. Here, we are focusing on the minimization of the aggregate volume of 3D bite the dust. In this paper, another initial topological structure is presented utilizing weighted coordinated chart of a floor planning issue in 3D VLSI physical plan. …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 6–17 Read article
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Performance Estimation of VLSI Design
Abstract: This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 59–66 Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 4, 2022 · pp. 42–54 Read article
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Delay Analysis for VLSI Interconnect’s Circuits
Abstract: This research work has been comprised of three parts. The first part deals with the implementation and estimation for the delay of an inverter and study of the influence of the delay variations with the increased size of the inverter. In this modern era of VLSI integrated circuits, interconnect’s delay majorly influences the device delay. The second phase of the work emphasizes on the realization of the interconnect delay and …
Published in Journal of Electronic Design Technology · Vol. 6, Issue 3, 2015 · pp. 25–32 Read article
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VLSI Transistor and Interconnect Scaling Overview
Abstract: In this paper, various types of device and interconnect scaling used for VLSI transistors are mentioned. Advanced device scaling techniques using SOI & FINFET technology are discussed for nano-devices. New technologies adopted at research level are stated here in brief. Keywords: Scaling factor ‘s’, technology or process node, short-channel effects, draininduced barrier lowering, punch through, surface scattering, velocity saturation, impact ionization, hot electrons, SOI, floating body, FinFET, quantum dot cellular …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 1–15 Read article
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Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETs in Nanoregime
Abstract: In this paper, performance of the VLSI circuits designed with strained silicon MOSFETs is analysed andcompared with bulk MOSFET. Emphasis is being given on the evaluation of speed, power and noisecharacteristics. An inverter circuit designed with single channel and dual channel biaxial strained MOSFETsof 40 nm channel length and 0.3 germanium mole-fraction is being taken to evaluate the performance throughsimulation. The device design and circuit simulation is done in Sentaurus …
Published in Journal of VLSI Design Tools and Technology · Vol. 1, Issue 1-2-3, 2011 · pp. 15–20 Read article
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Organic Material Based Device of VLSI :Solar Cell
Abstract: This focuses on one of the organic material-based devices of VLSI, which is Solar Cell, an electrical device that absorbs and converts the light energy precisely into electricity. This operates through the absorption of light which produces the pairs of electron-hole. After which it operates through the separation of charge carriers of the opposite one and lastly the separation of those carriers originates to a circuit. This covers the overall …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 3, 2019 · pp. 16–20 Read article
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Design of Decoder Using Domino Logic Circuit for VLSI
Abstract: Dissipation of power from a circuit is the major issue in the design of any VLSI circuit, which decreases the life span of a device/system. NMOS and PMOS circuits are very slow while switching the state from low to high. The speed of the circuit can be increased by decreasing resistance. This process in turn increases the static power dissipation. So, because of these disadvantages, CMOS circuits are used in …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 42–54 Read article
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Exploring the Potential of Adiabatic Logic for Low Power Nano-scale VLSI Designs
Abstract: Low power dissipation has emerged as one of the main research areas due to the ongoing scaling down of device technology in the area of VLSI circuit design. Adiabatic logic gates are a practical answer to the rising demand for low power portable gadgets. Various adiabatic logic families, including 2N-2N2P, PFAL (Positive Feedback Adiabatic Logic), DCPAL (Differential Cascode and Pre-resolved Adiabatic Logic), and a suggested circuit centred on the PFAL …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 1, 2023 · pp. 6–14 Read article
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A Novel Efficient VLSI Architecture of Modified 16B SQRT Carry Select Adder:A Review
Abstract: Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 3, Issue 2, 2015 · pp. 23–26 Read article
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Defect Detection in Patterned Fabrics Using Local Binary Pattern and Its VLSI Implementation
Abstract: For texture classification in computer vision Local Binary Patterns (LBP) is used as one of the efficient method. In this paper, LBP texture operator is used to label the pixels of an image of any fabric or texture using the property of thresholding the neighborhood of each and every pixel and considers the compared result as a binary number or a digit which will be used for detecting the defects …
Published in Journal of Microcontroller Engineering and Applications · Vol. 1, Issue 1, 2015 · pp. 45–51 Read article
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VLSI Implementation of Bit/Digit Serial-Parallel Finite Field GF (2m) Multiplier Using Standard Basis
Abstract: A Finite Field is a field with finitely number of elements. It is also known as Galois field in which the elements can take q different values is referred as GF (q).Finite fields are of great interest in applications like Elliptic Curve Cryptography (ECC), error control and coding. In this paper, we present a simple implementation of finite field GF (2m) multiplier. Here the main aim is to enhance the …
Published in Journal of Semiconductor Devices and Circuits · Vol. 1, Issue 3, 2014 · pp. 1–6 Read article
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Comparative Analysis of MOSFET, CNTFET and NWFET for High Performance VLSI Circuit Design: A Review
Abstract: Nanowires are inimitable materials for considering phenomenon in nanoscale regime. Nanowires development exhibits ample of applications by controlling their, structure, composition as well as their electrical properties. This paper review diverse types of nanowires, nanowire field-effect transistor (NWFET) structure and their comparison with novel devices. Firstly, this paper describes different types of nanowires and nanowire heterostructure that shows nanowire heterostructures eliminates various factors that limit the performance of homogeneous nanowire …
Published in Journal of VLSI Design Tools and Technology · Vol. 6, Issue 2, 2016 · pp. 19–32 Read article
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Reduce the Leakage Current and Power in VLSI Technology
Abstract: Demand for portability Reduce and increase in size, low cost, low dynamic power, low leakage current, low sub threshold current, and the necessity to minimise at least one of these. Circuit complexity increases with circuit integration. Memory and microprocessors are included in mass-produced chips. Microcomputer systems central system memory uses dynamic random-access memory (DRAM). One benefit of DRAM memory is its high speed and capacity integration. The examination of DRAM …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 3, 2023 · pp. 19–25 Read article
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A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction
Abstract: Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 3, 2022 · pp. 7–18 Read article
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Analysis and Characterization of Circuits for Leakage Power Reduction at Sub-50 nm in CMOS Circuits
Abstract: This paper analyzes various techniques to decrease leakage power in complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) circuits, because due to continuous scaling of CMOS technology there is improvement in speed of semiconductor devices and the side effect of this scaling is leakage power. With the development of technology in CMOS VLSI Circuit, length of transistors has been reduced and speed of operation is increasing simultaneously. As …
Published in Journal of Electronic Design Technology · Vol. 13, Issue 2, 2022 · pp. 11–22 Read article
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An Efficient Counter Using Modified Upper and Lower SVL Techniques and TSPCL
Abstract: Low power VLSI has emerged as the fundamental building block of the modern electronic era. This leads to a substantial paradigm shift where both power dissipation, performance and area of utmost importance. In the earlier time of fabrication, power dissipation was mainly neglected due to low device density and low operating frequency needed for computation. But in modern technological era, the need for high device density, higher operating frequency, proliferation …
Published in Research & Reviews : Journal of Physics · Vol. 13, Issue 2, 2024 · pp. 37–43 Read article
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A Majority Function Based Full Subtractor
Abstract: In the present landscape of very large-scale integration (VLSI) technology, the imperative to implement Boolean functions with minimal gate count remains a cornerstone of efficient circuit design. This pursuit has only grown more critical with the evolution of low-power design strategies, which now offer significantly enhanced benefits compared to traditional approaches. The trifecta of performance, affordability, and dependability continue to drive innovation in this field, shaping the trajectory of technological …
Published in Research & Reviews : Journal of Physics · Vol. 13, Issue 2, 2024 · pp. 8–14 Read article
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High Performance Multi-Valued Logic (MVL)Gate Design Using FinFET
Abstract: CMOS scaling faces challenges such as leakage, power dissipation, and short channel effects. Multi-Valued Logic (MVL) offers higher information density and reduced interconnections. This work presents a FinFET-based MVL gate design that improves electrostatic control, switching speed, and reliability. Simulation results confirm reduced leakage power and enhanced performance compared to conventional logic. The proposed architecture demonstrates scalability for advanced technology nodes. It also shows potential for low-power applications in portable …
Published in Journal of Microelectronics and Solid State Devices · Vol. 13, Issue 1, 2026 · pp. 34–45 Read article