STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Electronic Design Technology

VLSI Transistor and Interconnect Scaling Overview

  1. Pritam Bhattacharjee
  2. Arindam Sadhu

Abstract

In this paper, various types of device and interconnect scaling used for VLSI transistors are mentioned. Advanced device scaling techniques using SOI & FINFET technology are discussed for nano-devices. New technologies adopted at research level are stated here in brief. Keywords: Scaling factor ‘s’, technology or process node, short-channel effects, draininduced barrier lowering, punch through, surface scattering, velocity saturation, impact ionization, hot electrons, SOI, floating body, FinFET, quantum dot cellular automata
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