STM Journals Peer-reviewed research from Consortium e-Learning Network

4 publications

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    VLSI Transistor and Interconnect Scaling Overview

    By Pritam Bhattacharjee, Arindam Sadhu

    Abstract: In this paper, various types of device and interconnect scaling used for VLSI transistors are mentioned. Advanced device scaling techniques using SOI & FINFET technology are discussed for nano-devices. New technologies adopted at research level are stated here in brief. Keywords: Scaling factor ‘s’, technology or process node, short-channel effects, draininduced barrier lowering, punch through, surface scattering, velocity saturation, impact ionization, hot electrons, SOI, floating body, FinFET, quantum dot cellular …

    Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 1–15 Read article

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    Performance Estimation of VLSI Design

    By Pritam Bhattacharjee

    Abstract: This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.

    Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 59–66 Read article

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    Methodology of Standard Cell Library Design in .LIB Format

    By Pritam Bhattacharjee

    Abstract: The importance of standard cell library design methodology is growing with very-large-scale integration (VLSI) technology advancement due to its usage in VLSI EDA synthesis flows. In this paper, to best of our knowledge and information in any published literature no systematic method of standard cell and creating appropriate co-laterals. In this paper the standard cell design methodology, layout topology, methodology for creating characterized timing table has been developed using 250 …

    Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 1, 2014 · pp. 30–38 Read article

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    SPICE Modeling of LDMOSFET Transistor

    By Pritam Bhattacharjee

    Abstract: AbstractHigh voltage integrated circuits, these days are the most viable alternatives to discrete circuits for various applications. The popular amongst them is the lateral double diffused MOS transistor (LDMOS). It is based on the lightly doped drain (LDD) concept. The constraint that occurred in modeling LDMOS is to minimize the on-resistance along with maintaining a high breakdown voltage. To achieve the objective, the help of RESURF (Reduced Surface Field) concept …

    Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 1, 2016 · pp. 42–57 Read article

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