Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing demand of high speed and low power consumption processor. Speed of processor greatly depends on its multiplier as well as adder performance. Due to which high speed adder architecture become important. Several adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we introduce an architecture of high speed modified carry select adder using booth encoder (BEC) Technique. The proposed design has reduced area and power as compared with the regular SQRT CSA .Booth encoder, Mathematics is an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs are implementated on Xilinx Vertex device family.The results analysis shows that the proposed CSA structure is better than the regular SQRT CSA.
