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Research & Reviews : Journal of Physics Original Research

A Majority Function Based Full Subtractor

  1. Angshuman Chakraborty Department of Electronics and Communication, Tripura Institute of Technology
  2. Tanmoy Baraj Department of Electronics and Communication, Tripura Institute of Technology

Abstract

In the present landscape of very large-scale integration (VLSI) technology, the imperative to implement Boolean functions with minimal gate count remains a cornerstone of efficient circuit design. This pursuit has only grown more critical with the evolution of low-power design strategies, which now offer significantly enhanced benefits compared to traditional approaches. The trifecta of performance, affordability, and dependability continue to drive innovation in this field, shaping the trajectory of technological advancements across various sectors. Of particular importance is the escalating recognition of power dissipation as a pivotal factor in shaping competitive markets, such as those for wireless applications, laptops, and portable medical equipment. As consumer demand for efficiency and longevity in battery-powered devices intensifies, reducing power consumption has become synonymous with improving product usability and market competitiveness. This paper contributes to this ongoing discourse by focusing on the comparative analysis of multiple full subtractor circuits, evaluating their transistor count and overall power consumption. Central to our investigation is the introduction of a novel full subtractor design based on majority logic, which promises substantial advancements over established methodologies. By leveraging the inherent advantages of majority logic, our proposed circuit aims to streamline operations, minimize gate complexity, and ultimately enhance power efficiency—a critical consideration in contemporary VLSI design paradigms. Through meticulous experimentation and comparative study, we highlight the distinct advantages of our proposed majority logic-based full subtractor. Not only does it exhibit a reduced transistor count and lower power consumption compared to traditional designs, but it also demonstrates robust performance metrics across varying operational conditions

Keywords

References (11)

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