STM Journals Peer-reviewed research from Consortium e-Learning Network

Journal of Microelectronics and Solid State Devices Original Research

Design of Optimized Full Adder using Noise-Mitigation Techniques and Power Gating

  1. Kushal Mandhyan Department of Electronics and Instrumentation Engineering, R V College of Engineering (An Autonomous Institution, Affiliated to VTU Belagavi), Bengaluru
  2. Kushal Mandhyan Department of Electronics and Instrumentation Engineering, R V College of Engineering (An Autonomous Institution, Affiliated to VTU Belagavi), Bengaluru

Abstract

With the advent of nanoscale technology, a new era of power consumption, speed, and reliability challenges for traditional static CMOS logic has begun. To solve these problems, dynamic logic families—particularly domino logic—have emerged as potent substitutes that offer quicker processing speeds and lower power consumption. The design and optimization of a full adder circuit using domino logic is shown in this study. A dynamic domino logic technique is used to build the proposed full adder architecture, utilizing the benefits of the precharge and evaluate phases to improve performance. This work investigates the design and optimization of a complete adder circuit utilizing the domino logic dynamic logic paradigm, which stands out for having distinct precharge and evaluate stages. To maximize the inherent advantages of domino logic, our design integrates cutting-edge noise mitigation techniques like power gating, noise margin analysis, and synchronous clocking. Apart from capitalizing on the intrinsic benefits of domino logic, the suggested architecture integrates power gating, noise margin analysis, and synchronous clocking to tackle issues related to noise and power usage. A significant percentage of noise and power reduction is noticed.

Keywords

References (10)

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