CMOS
6 articles · search the full text for this term
-
Design and Implementation of High-Speed Low Power Low Area Hybrid One Bit Full Adder Using CMOS Technology
Abstract: In this article, we'll take a look at a new kind of Full Adder (FA) design that mixes traditional Complementary Metal Oxide Semiconductors (CCMOS) with Pass Transistors (PTs) and Transmission Gates (TGs). To analyze the circuit's performance, we used the Mentor Graphics software package. Since all twenty (20) varieties of Full Adder circuits were able to be measured and compared, this research was conducted. When the clock rate of the …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 29–39 Read article
-
Design and Implementation of Low Noise Power Low and High Speed Three Stage Comparator Using 16nm Technology
Abstract: To meet the demands of quicker operation and reduced noise levels, this study proposes a new CMOS Three-based comparator version. Efficiency may be significantly improved by comparing the suggested model to existing ones. This is so because the suggested comparator would improve the efficiency of the current amplifier design. The suggested model drives the input pairs of the regenerator and the amplified stage, making for a quicker comparator. The structure …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 10–16 Read article
-
QCA-based Implementation of Budget-friendly and Energy-Efficient Exclusive-OR/Exclusive-NOR Gates
Abstract: Quantum-dot cellular automata (QCA) is a novel nanoscale computational approach that proposes reduced dimensions, lower power consumption, increased speed, and deliberate design as a solution to the scaling challenge associated with CMOS technique. QCA is a nascent nanotechnology that utilizes the Coulomb repulsion principle. Quantum computing has emerged as a highly effective paradigm for the creation of energy-efficient hardware at the nanoscale. This article presents implementation of a very efficient …
Published in International Journal of Electro-Mechanics and Material Behaviour · Vol. 1, Issue 2, 2023 · pp. 1–6 Read article
-
Design and Simulation of Low-power, High-speed Effective Area Mux Based One-bit Full Adder Using CMOS Technology
Abstract: Our findings reveal a novel kind of circuit capable of performing both XOR and XNOR operations in parallel. Power dissipation and delay are both greatly reduced in the proposed circuits due to their low output capacitance as well as minimal short-circuit power dissipation. We show six new hybrid 1-bit full-adder (FA) circuits that take use of the XOR-XNOR or XOR/XNOR gates' special full-swing function. Each potential circuit layout has both …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 25–33 Read article
-
Design and Implementation of Low-power SPI Shift Register
Abstract: SPI stands for serial peripheral interface which is used for serial, synchronous and full duplex communication of data between master and slave devices. Master devices can be Microprocessors or Microcontrollers; and slaves are the Peripheral devices interfaced with them. The main internal component for architecture of master/slave block is shift register which defines its operation. But as the size of the shift register increases, power is utilized to a greater …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 1–15 Read article
-
Design and Implementation of Low Power and Area Efficient Sub Threshold Level Shifter Using 16 nm CMOS Technology
Abstract: An efficient method of modifying subthreshold voltages is proposed here. As an alternative to static power dissipation, the suggested design allows for charging of internal nodes through VDDH. The force of the pull-down mechanism may be increased by connecting a second auxiliary circuit. The transition energy for input frequencies between 1 and 5 MHz is 84 fJ, the propagation delay is 46 ns, the dynamic power dissipation is 0.3 mW, …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 1, 2023 · pp. 16–24 Read article