Power-Efficient Design Strategies for Static Random Access Memory with Memory Blocks: A Review

Biswaranjan Barik; P. V. Dileep Bhumireddi

doi:10.37591/jomea.v10i3.7770

Abstract

For many years, CMOS technology has been able to achieve high integration density and great performance by scaling down its feature size and threshold voltage. Power consumption has been a major concern in VLSI design due to the ongoing drop in aspect ratio and the related improvements in chip density and operation frequency. SRAM is a type of random-access memory in which an interruption in power causes data loss. For conserving each bit, a flip flop is used. Static RAM and dynamic RAM are different in that data in SRAM is stored forever while power is present, whereas data in DRAM ages exponentially. SRAM doesn't need a refresher circuit and provides a straightforward data accessmechanism. When everything is working well, SRAM performs very well and uses less power; nevertheless, when reading and writing, it uses more power. The outline designs of Static Random Access Memory (SRAM) with six and eight transistors for minimal power consumption are shown in this study. By lowering the voltage at the output node, the SRAM can operate at low power. The 4-BIT memory block with an 8-T architecture was created utilising 90 nm technology and a 1.2V supply voltage. It is implemented with a custom compiler and the Synopsys tool.

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