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23 articles for “arithmetic unit”
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Coarse-grained Logic Interface with Floating-point Arithmetic Unit: A Review
Abstract: One of the key elements of their design, which has a substantial impact, is their choice of programmable connectivity and logic capabilities. The FPGA architecture has a significant impact on the speed performance, space efficiency, and power consumption of the finished device. This examination examines the evolution of programmable logic devices over time, the underlying programming paradigms that underpin programmability, and the most important findings from architectural system research. We …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 11, Issue 2, 2023 · pp. 18–24 Read article
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Study And Literature Analysis of The Coarse-Grained Logic Interface with Floating-Point Arithmetic Unit
Abstract: Field-Programmable Gate Arrays (FPGAs) have become an essential digital circuit implementation techni que. The research looks at the design parameters by evaluating the building of an arithmetic logic unit (ALU) in Xilinx Vivado utilizing Hardware Description Language (HDL) and implementing common Field Programmable gate arrays (FPGAs). The ALU is a logic design component in digital computers that seeks to deliver optimal algorithms to maximize the usage of available hardware. The …
Published in Journal of VLSI Design Tools and Technology · Vol. 13, Issue 2, 2023 · pp. 45–55 Read article
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Swing Restored Low Power and Area Efficient 8-bit Arithmetic Logic Unit Using Modified Gate Diffusion Input Technique
Abstract: AbstractThe arithmetic logic unit (ALU) is one of the most fundamental operational units in any processor. The ALU is the heart of any system or any processor and the core component of the central processing unit because mainly all the fundamental operations are performed by the help of ALU only. So, it can be defined as the combinational unit that is used to perform its logical and arithmetic units. The …
Published in Journal of Microcontroller Engineering and Applications · Vol. 5, Issue 2, 2018 · pp. 19–29 Read article
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Area and Speed Efficient Floating Arithmetic Logic Unit Implementation on Hybrid FPGAS
Abstract: Proposed design of an Area and Speed optimized field arithmetic logic unit (FALU) for modern computing of advanced processors, as we are aware that in most of the DSP (Digital Signal Processors) FALU is a critical component for continuous calculation of signs and ongoing information to meet the constant situation of sign handling it is exceptionally needed to make calculation quicker as could be expected so we have thought of …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 9, Issue 3, 2021 · pp. 29–34 Read article
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High Throughput RISC Processor Design Using Vedic Mathematics: A Review
Abstract: The load on general processor is increasing. It is of the utmost importance in the arithmetic unit for fast operations. Multipliers have a significant impact on how well the Arithmetic Unit performs. In this way, analysts are constantly looking for new methodologies and equipment to execute number juggling activity in tremendous proficient manner in the terms of speed and region. Vedic Science is the old arrangement of math which has …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 2, 2022 · pp. 29–33 Read article
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Implementation of Carry Select Adder with Reduced Area Scheme
Abstract: Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So, adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry select adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 1, 2017 · pp. 1–5 Read article
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Reducing Crosstalk in Arithmetic and Logic Unit Part of a Processor
Abstract: Crosstalk is common in any digital systems and may occur due to coupling of signals which eventually have an impact on the working of a system. In this paper, an attempt is made to study the effect of crosstalk in 8-bit slice ALU, designed using 120 nm technology and suggested a method to reduce the crosstalk.Keywords: ALU, signal integrity, metal layers
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 1, 2013 · pp. 28–32 Read article
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A Simple, Compact, and Power-Efficient Current-Mode Decimal Adder Circuit
Abstract: A size and power efficient current-mode decimal adder is proposed in this paper. The proposed adder does not use binary coded decimal (BCD) number system for processing the decimal data like other decimal adders. Instead, it processes the decimal data as the actual decimal inputs. The proposed adder can be used as a decimal half adder as well as a decimal full adder. The adder is based on simple decimal …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 18–23 Read article
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64 Bit ALU DESIGN USING VEDIC MATHEMATHICS
Abstract: High-speed arithmetic operations are crucial for better performance in contemporary digital systems. Particularly for high bit-width operations, conventional arithmetic logic units (ALUs) frequently experience increased latency and complexity. This work presents the design and implementation of a 64-bit Arithmetic Logic Unit (ALU) using notions from Vedic mathematics. The suggested design makes use of a Kogge-Stone Adder for effective addition and the Urdhva Tiryagbhyam sutra for quick multiplication. Among other mathematical …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 4, Issue 1, 2026 Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article
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Design and Implementation of A 4-bit Multiplier using Wallace Tree Architecture in 180 nm Technology
Abstract: Over the period of last decade, power dissipation has become one of the most important factors for VLSI designers in the design of most digital systems. Even though the speed and area are considered to be the critical factors in design of digital systems, there is a trade of with power consumption. Adders and multipliers are the most important arithmetic units in a processor and the major sources of power …
Published in Journal of Microcontroller Engineering and Applications · Vol. 2, Issue 1, 2015 · pp. 17–23 Read article
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Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder
Abstract: The ALU is one of the most frequently accessed modules in a CPU and is utilized during most instruction executions. Hence the power consumption of the ALU is a major concern. In this paper a low power 32 bit ALU is designed using VHDL. Lower power consumption is achieved by using clock gating technique than conventional design. A carry skip adder with variable block length is used for the arithmetic …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 2, 2013 · pp. 6–11 Read article
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A Novel Design for High Speed & Area Efficient Compressor Based Vedic Multiplier
Abstract: Multipliers are the most important part in any arithmetic and logic unit, AbstractMultipliers are the most important part in any arithmetic and logic unit, accumulators and digital signal processors. Due to the increasing constraints on delay, the design of faster multipliers is emphasized. Among several multipliers, Vedic multipliers are preferred for their speed of operation. Here the proposed Vedic multiplication techniques are based on “URDHVA TIRYAKBHYAM” a fast and efficient …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 3, 2018 · pp. 1–10 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level
Abstract: Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 3, 2021 · pp. 10–18 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute-intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered by …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 2, 2022 · pp. 22–33 Read article
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Building Knowledge with a Hands-on 8-bit CPU Architecture Simulation Kit for Students
Abstract: It is now crucial for students studying electronics and information technology to comprehend computer architecture and logic design. Hands-on, practical instruction is required to assist students in understanding Computer Organization and Architecture (COA). Our kit, which covers essential components including bus interfaces, arithmetic, and logic units (ALU), memory structures, and functional registers, is based on the Von Neumann architecture. Theoretical techniques like block diagrams and top level diagrams are typically …
Published in Journal of Electronic Design Technology · Vol. 15, Issue 3, 2024 · pp. 1–9 Read article
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An Area Delay Optimized Carry-Select Adder
Abstract: In arithmetic and logic unit of digital signal processor (DSP), adder is the important hardware unit. Carry select adder (CSLA) is the best example of the adder used in DSP and it is widely used in many data processors to increase speed. So, the adder performance affects the overall system-performance. The Regular Square root (SQRT) CSLA consists of two Ripple Carry Adders (RCA), so it consumes more area due to …
Published in Journal of VLSI Design Tools and Technology · Vol. 8, Issue 3, 2018 · pp. 10–14 Read article
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A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture
Abstract: A multiplier is a fundamental block of any digital signal processing system. Urdhva Tiryakbhyam sutra, from ancient Indian Vedic mathematics, offers regular and hierarchical multiplier architecture. Alternatively, current-mode multi-valued logic results in reduced circuitry and effective utilization of interconnections. In this paper, a new 4×4 current-mode quaternary Vedic multiplier design is proposed. The multiplier has been simulated using 0.18 µm technology with a power supply of 1 V and a …
Published in Journal of VLSI Design Tools and Technology · Vol. 4, Issue 2, 2014 · pp. 37–46 Read article