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34 articles for “power delay product”
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Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes
Abstract: This paper presents a power-aware high-performance design of ternary combinational and sequential circuits based on carbon nanotube field effect transistor (CNFET) using ternary logic. Carbon nanotube based field effect transistor (CNFET) are being studied extensively as a possible and promising choice for nanoscale integration and as successor to complementary metal oxide semiconductor (CMOS) devices. Ternary logic circuit has attracted substantial interest due to its simplicity, energy efficiency, and reduced interconnect …
Published in Journal of VLSI Design Tools and Technology · Vol. 3, Issue 3, 2013 Read article
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Transistor Full Adder: A Comparative Performance Analysis
Abstract: AbstractIn this work the static energy recovery full adder named 10T13A with reduced 10 transistors is implemented. The fan in and fan-out of gates is also reduced by reducing number of transistors. Calculation of 10T13A full adder various parameters has been at 45 nm technology and compared with MTCMOS technique based 10T13A Full Adder. The active power has been calculated at 45 nm technology using Cadence Virtuoso Tool. Simulation results …
Published in Recent Trends in Electronics Communication Systems · Vol. 5, Issue 3, 2018 · pp. 22–31 Read article
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Design of Energy Efficient Clock System
Abstract: Energy efficiency is a key metric for energy constrained Ultra Low Power (ULP) VLSI applications such as wireless sensor nodes, pace makers, hearing aids etc. These applications need clock system in their signal processing and communication sub-system. Moreover, clock system plays a vital role in governing the reliability, power consumption and performance of synchronous system. In today’s era of portable electronics, power consumption has emerged as a forefront design metrics. …
Published in Journal of VLSI Design Tools and Technology · Vol. 9, Issue 2, 2019 · pp. 1–7 Read article
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Hybrid CMOS-SET Inverter Design for Improved Performance using Tied Body-backgate Technique
Abstract: Single-electron transistors (SETs) are an attractive candidate for future functional elements in LSIs, because of their low-power consumption and small size. Integration of current CMOS technology with the emerging SET devices is an effective approach for improving density of integration in VLSI chips and ensuring ultra low power dissipation along with the advantages of CMOS technology like high gain, current drive, speed and matured fabrication technology. This paper investigates hybrid …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 1, 2015 · pp. 24–29 Read article
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Analysis of 2-Stage Inverter Delay Line with Supply Voltage Variation
Abstract: Nowadays, the performance parameters should not affect the variation in fixed parameters like leakage current, leakage power, propagation delay, and power delay product. So this study is basically focused on the effects of changes in supply voltage (0.8–1.2V) on the various performance parameters of 2-stage inverter based delay line based on CMOS architecture. A delay line is a discrete element in digital theory, which simply allows a signal to be …
Published in Trends in Electrical Engineering · Vol. 9, Issue 1, 2019 · pp. 31–35 Read article
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Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style
Abstract: A different logic style including the constant logic style is proposed in this paper which is helpful in increasing the high speed applications. It is suitable for implementing the complicated arithmetic expressions. The objective of this paper is to reduce the delay, noised margin and power consumption. The transistor for minimal power delay product and energy delay product is proposed in this paper. The design and implementation of adder in …
Published in Journal of VLSI Design Tools and Technology · Vol. 5, Issue 2, 2015 · pp. 38–41 Read article
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Design and Simulation of Ternary Gates Using Fin-FET
Abstract: In recent years, digital communication system has becomes more popular. But the on-chip interconnections have become a major problem as more and more modules are packed into a chip by reducing the gate size. As the gate size is reduced further the complexities in the circuit increases. Binary logic circuit dissipates a lot of energy, increase processing time, and causes coupling effect. In the Ternary logic system, there are three …
Published in Journal of Semiconductor Devices and Circuits · Vol. 2, Issue 3, 2015 · pp. 4–18 Read article
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Design and Simulation of Full Adder-Based CMOS 4-2 Compressor using CMOS XOR-XNOR Logic
Abstract: This study utilizes the recent development of CMOS transistors to construct an energy-efficient Full adder-based CMOS 4-2 compressor. The CMOS Exclusive-OR-Exclusive-NOR component and multiplexer used in the transmission logic of the novel CMOS compressor include eight transistors. The XOR-XNOR logic style is the most efficient and effective due to its speed and reduced power consumption. Utilizing an operational supply voltage of 0.7 V and 90nm CMOS technology, the Cadence Virtuoso …
Published in Recent Trends in Electronics Communication Systems · Vol. 12, Issue 3, 2025 · pp. 1–8 Read article
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Optimizing the Ratio of Number of Tubes in PCNTFET to NCNTFET for Digital Circuits
Abstract: AbstractCarbon nanotube Field Effect Transistors (CNTFET) offer various benefits as compared to other FETs. Many circuits can be constructed using PCNTFETs (P-type CNTFET) and NCNTFETs (N-type CNTFET) similar to the PMOS and NMOS of the CMOS technology. The CNTFETs employ carbon nanotubes in the channel of the device to provide a path for the ballistic conduction of electrons. The different ratios of number of tubes in channel of the PCNTFET …
Published in Journal of Microelectronics and Solid State Devices · Vol. 5, Issue 1, 2018 · pp. 34–40 Read article
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Improvement of Design Issues in FinFET based Design Techniques for XOR and XNOR Circuits at 45 nm Technology
Abstract: The scaling of conventional CMOS circuit inclines to the short channel effect due to leakage current increase in the circuit. To minimize the short channel effect, FINFET can be used in place of conventional CMOS circuits. This paper demonstrates comparative performance study of high speed, low power and low voltage on XOR and XNOR digital circuit. This paper assesses and compares the performance of XOR and XNOR logic circuits. This …
Published in Journal of Electronic Design Technology · Vol. 5, Issue 1, 2014 · pp. 22–35 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute-intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered by …
Published in Journal of VLSI Design Tools and Technology · Vol. 12, Issue 2, 2022 · pp. 22–33 Read article
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A Circuit Approach for CMOS VLSI Circuit Leakage Power Reduction
Abstract: Despite the fact that scaling CMOS technology boosted speed, leakage currents always remained an issue. The issue has gotten worse as the scaling has gone into the UDSM (ultra-deep-submicron) range. In order for the circuit to function effectively, these unwanted leakage currents must be reduced to a minimum. It is challenging to create these leakage-free nano-scale CMOS circuits. In this work, the issue of leakage power is addressed, which occurs …
Published in Research & Reviews: A Journal of Embedded System & Applications · Vol. 10, Issue 3, 2022 · pp. 7–18 Read article
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Design and Performance Analysis of Full Adder Cell using FinFET Technique at 32nm Technology
Abstract: AbstractIn this paper, discussed is the comparative analysis of complementary MOS (CMOS) and dual gate-FinFET (fin shaped field effect transistor) based full adder cell design. To reduce the average power, average current and maximum current of 1-bit full adder circuit a new high DG-FinFET technique is presented. Use of double-gate FinFET technology provides low leakage and high performance operation. For MOSFET transistor model, a predictive technology model (PTM) BSIM4 and …
Published in Journal of Microelectronics and Solid State Devices · Vol. 4, Issue 3, 2017 · pp. 1–8 Read article
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Design of a Multipurpose Ternary Arithmetic Circuit Using CNTFET
Abstract: AbstractIn this paper, a multipurpose ternary arithmetic circuit is presented for ternary processors based on carbon nanotube field effect transistors (CNTFETs). Both addition and subtraction can be performed using same circuit’s configuration, which is the special feature of the proposed circuit. The combination of pseudo and complimentary logic structure are employed to blend the binary and ternary logic techniques. The propagation delay and power delay product are 139.5 pico second …
Published in Journal of Semiconductor Devices and Circuits · Vol. 3, Issue 1, 2016 · pp. 13–24 Read article
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Performance Analysis of Schmitt Trigger Circuit for Noise-Free Chips
Abstract: At lower nodes of complementary metal-oxide semiconductor (CMOS) technology, noise within a chip increase due to a drastic increment in interconnects within a given area. To improve the noise immunity of a chip, a Schmitt trigger circuit is used as a buffer instead of a simple CMOS inverter at various intervals along the metal interconnect. The use of a Schmitt trigger circuit not only makes the chip noise immune but …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 11–20 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 2, 2017 · pp. 55–60 Read article
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Single Bit Low-Power High-Speed Full Adder
Abstract: This paper presents a high-speed low-power full adder cells that lead to have a reduced power-delay product (PDP). A comparison against other full-adder structure as having low PDP, in terms of speed, power consumption and area of cells is carried out. This paper contains, a hybrid 1-bit full adder design employing both complementary metal-oxide semiconductor (CMOS) and transmission gate logic styles. First implemented was the design for 1 bit then …
Published in Journal of VLSI Design Tools and Technology · Vol. 7, Issue 3, 2017 · pp. 55–60 Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article
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A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic
Abstract: This paper presents a method to designing Various Adder Circuits using CMOS Logic Style for Energy-Efficient Arithmetic Applications. We present Ripple Carry Adder, Carry Bypass Adder, Carry Look Ahead Adder and Carry Skip Adder in CMOS logic styles that lead to have reduced power-delay product (PDP). We executes a comparison against each other adders which finally provide result as having a low PDP, with reference to power consumption, speed and …
Published in Journal of VLSI Design Tools and Technology · Vol. 11, Issue 2, 2021 · pp. 24–34 Read article