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181 articles for “delay”
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Advancements in Satellite Networking Applications Through Delay-tolerant Networking (DTN)
Abstract: The burgeoning demand for global connectivity and communication has intensified the exploration of novel networking paradigms, especially in remote or challenging environments where traditional methods fall short. One such innovative approach is delay-tolerant networking (DTN), a technology specifically engineered to work in scenarios where standard networking is unreliable, frequently disrupted, or suffers from considerable delays. This study focuses on the application of DTN in satellite networking, a domain characterized by …
Published in Journal of Advances in Shell Programming · Vol. 11, Issue 1, 2024 · pp. 24–28 Read article
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A Study on the Impact of GPS-Derived Tropospheric Delay over some Nigerian Stat
Abstract: The effect of GPS-derived tropospheric delay on radio propagation oversome Nigerian stations is examined. The stations are located in the African equatorial region, and include: Abuja (8.9°N, 7.4°E), Akure (7.3°N, 5.2°E), Enugu (6.5°N, 7.5°E), Lagos (6.5°N, 3.4°E), and Port Harcourt (4.8°N, 7.0°E). This is the first study in the African equatorial region that uses in-situ meteorology measurements as well as GPS satellite measurements to present the impact of tropospheric delay …
Published in Research & Reviews : Journal of Space Science & Technology Read article
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Delay Analysis of HS-14T 45nm CMOS SRAM with Different SRAM Techniques for Improvement in Speed
Abstract: This paper presents a novel HS-14T design aimed at significantly improving read and write delays compared to conventional 6T and other memory cells RHRD-12T, SEUH-12T, and NHRC-14T. As technology scales, the demand for faster and more stable memory cells becomes increasingly critical. Our proposed HS-14T incorporates additional transistors to enhance stability and reduce access times, resulting in notable performance gains. Comprehensive simulations reveal that the HS-14T SRAM cell substantially reduces …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 2, 2024 · pp. 1–13 Read article
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Evaluating Delay Impacts: From Root Cause Analysis to Dispute Resolution
Abstract: Construction projects inherently involve complex coordination among multiple stakeholders, interdependent tasks, and unpredictable external challenges, which frequently cause schedule overruns and disputes. Traditional contractual mechanisms—such as extensions of time (EoT), liquidated damages, and force majeure clauses—serve to define responsibilities, allocate risk, and establish formal dispute pathways when delays arise. For example, EoT provisions protect contractors from penalties when delays are beyond their control, provided proper notice and evidence are submitted …
Published in Journal of Structural Engineering and Management · Vol. 12, Issue 3, 2025 · pp. 11–25 Read article
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Twisting, Super Twisting and Adaptive Algorithm Sliding Mode Controller for Second Order Time Delay Systems
Abstract: The sliding mode control approach is widely considered as one of the most effective methods for designing a reliable controller for a complicated higher-order dynamic plant operating under uncertainty. The primary advantages of sliding mode is its low sensitivity to changes in plant parameters and the ability to entirely eliminate disruptions. Sliding mode control has been widely applied as a robust control design methodology that is completely insensitive to uncertainties, …
Published in Current Trends in Signal Processing Read article
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Mathematical Modeling of Tumor Growth and Immune System Interaction Incorporating Time Delays and Suppression Effects for Tumor Control
Abstract: Cancer growth is a complex biological process influenced by various factors, including the dynamic interaction between tumor cells and the host immune system. Mathematical modeling serves as a powerful tool to understand these interactions and predict the outcomes of different therapeutic strategies. This study presents a mathematical framework that captures the essential dynamics of tumor-immune interactions, specifically incorporating the effects of time delay and immune suppression mechanisms. Time delay accounts …
Published in Research and Reviews : A Journal of Immunology · Vol. 15, Issue 3, 2025 · pp. 25–34 Read article
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Lean Design Management as a Solution for Delays in Design Phase
Abstract: The results of this study reveal that traditional project management has a negative impact on the performance of construction projects and addresses its weaknesses in the design stage. Poor quality documentation from poorly managed design projects leads to budget overspending, delay, rework, and disputes. This paper emphasizes the importance of technical cooperation and highlights the lack of focus on value and waste in design development. Lean Design Management (LDM) is …
Published in International Journal of Architectural Design and Planning · Vol. 2, Issue 1, 2024 · pp. 30–39 Read article
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Comparative Study of Time Slice Windows Analysis and Impacted As-Planned Analysis for Data Center Construction Projects Using Primavera P6 24.12 Version
Abstract: Data centers are IT infrastructure that needs to be precisely scheduled and coordinated. Significant financial losses and operational failures may result from building delays. Stakeholders can assign blame and comprehend the reasons behind delays with the aid of forensic delay analysis. Because of their unique approaches and legal acceptability, TSWA, and IAPA are commonly used among the many strategies. These methods provide various ways to analyze project schedules and pinpoint …
Published in Journal of Construction Engineering, Technology & Management · Vol. 16, Issue 1, 2026 · pp. 33–51 Read article
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Investigating Factors Associated to Speech and Language Development Problem Among Under-five Children in Bangladesh: A Cross-Sectional Study
Abstract: Speech and Language Delay (SLD) is a developmental disorder characterized by a lag in a child's acquisition and use of spoken language compared to typical developmental milestones. It is a significant developmental concern with profound implications for cognitive, social, and academic outcomes. The objective of this study is to explore the factors associated to SLD in children and early intervention of the problem to support the children who need special …
Published in International Journal of Children · Vol. 2, Issue 2, 2025 · pp. 1–12 Read article
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Design And Optimization Of High-Speed Array Multiplier
Abstract: An array multiplier is a digital circuit used for the rapid multiplication of binary numbers. It employs an array of logic gates to generate partial products concurrently, significantly enhancing speed. The array structure divides the multiplication task into smaller, parallel processes, allowing for efficient parallel processing of multiple bits. Each cell within the array manages specific bit-level multiplications, and their results are summed to produce the final product. This parallel …
Published in Journal of Microelectronics and Solid State Devices · Vol. 11, Issue 3, 2024 Read article
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Identification and Assessment of the Factors causing Cost Overrun in Housing Projects
Abstract: Poor cost performance is a major problem in construction industry, especially in developing countries like India. Statistics reveal that majority of the projects faces the issue of cost overrun. The interrelationship between the causes of cost overrun and stakeholders has not been explored yet. The aim of the research is to minimize the effects of project cost overrun. The objective of the study is to categorize and rank the potential …
Published in International Journal of Urban Design and Development · Vol. 1, Issue 1, 2023 · pp. 17–34 Read article
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Performance Analysis of Schmitt Trigger Circuit for Noise-Free Chips
Abstract: At lower nodes of complementary metal-oxide semiconductor (CMOS) technology, noise within a chip increase due to a drastic increment in interconnects within a given area. To improve the noise immunity of a chip, a Schmitt trigger circuit is used as a buffer instead of a simple CMOS inverter at various intervals along the metal interconnect. The use of a Schmitt trigger circuit not only makes the chip noise immune but …
Published in Journal of VLSI Design Tools and Technology · Vol. 14, Issue 3, 2024 · pp. 11–20 Read article
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Performance Comparison of Noise-Tolerant, High- Performance CMOS Domino Logic Configurations
Abstract: In high-performance VLSI chip design, domino logic configuration is often preferred over static logic due to its faster operation and smaller area footprint, especially in deep submicron (DSM) technology. However, DSM noise has become a significant challenge in domino-based circuits, leading to compromises in the reliability and signal integrity of integrated circuits (ICs). The switching threshold of domino logic, defined as the input voltage level at which the gate output …
Published in Journal of Semiconductor Devices and Circuits · Vol. 12, Issue 2, 2025 · pp. 35–50 Read article
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Design and Analysis of Low-Power CMOS Inverter Chains for High-Speed Digital Circuits
Abstract: This report briefly explains the design process, structure, and evaluation of a CMOS inverter designed using a 45 nm technology process with a focus on its propagation delay and power consumption. Moreover, the CMOS inverter design will be created using the Cadence Virtuoso design environment, along with a post-layout analysis of the design. Performance evaluation of the designed circuit will be carried out through the execution of a transient analysis …
Published in Journal of VLSI Design Tools and Technology · Vol. 16, Issue 1, 2026 · pp. 40–57 Read article
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Effect of Leading-Edge Roughness on the Aerodynamic Characteristics of the Wind Turbine blade
Abstract: Leading-Edge Roughness (LER) strongly dictates boundary layer transition and performance degradation on an airfoil operating at transitional Reynolds numbers, an aerodynamic regime where shear-layer stability mechanisms remain highly complex. The wind tunnel experiments were conducted to investigate the aerodynamic impacts of surface roughness applied over 25% of the chord of a NACA 0018 airfoil using two discrete roughness gradations. Surface roughness induces an early boundary layer trip, causing elevated section …
Published in Journal of Aerospace Engineering & Technology · Vol. 16, Issue 2, 2026 Read article
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Design and Simulation of Full Adder-Based CMOS 4-2 Compressor using CMOS XOR-XNOR Logic
Abstract: This study utilizes the recent development of CMOS transistors to construct an energy-efficient Full adder-based CMOS 4-2 compressor. The CMOS Exclusive-OR-Exclusive-NOR component and multiplexer used in the transmission logic of the novel CMOS compressor include eight transistors. The XOR-XNOR logic style is the most efficient and effective due to its speed and reduced power consumption. Utilizing an operational supply voltage of 0.7 V and 90nm CMOS technology, the Cadence Virtuoso …
Published in Recent Trends in Electronics Communication Systems · Vol. 12, Issue 3, 2025 · pp. 1–8 Read article
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Machine Learning-Based Channel Estimation in 5G, Beyond-5G, and 6G Networks: Recent Advances and Future Directions
Abstract: Accurate channel estimation is one of the most fundamental challenges in modern wireless communication systems. In fifth- generation (5G) New Radio (NR) and emerging sixth-generation (6G) networks, precise knowledge of the wireless channel is essential for achieving reliable data transmission, high spectral efficiency, and low Bit Error Rate (BER). Conventional estimation techniques such as Least Squares (LS) and Minimum Mean Square Error (MMSE) rely on mathematical channel models and predefined …
Published in Journal of Telecommunication, Switching Systems and Networks · Vol. 13, Issue 2, 2026 Read article
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Comparative Analysis of CMOS CNFET and Memristor Based Full Adder Circuits and CMOS Memristor Based Multiplexer Circuits
Abstract: Continued developments in microelectronics technology have led to a myriad of new compute- intensive applications at the micro-edge, such as artificial intelligence and signal and image processing. Multiplication is a crucial arithmetic process in such applications. However, large logic complexities typically seen in traditional multipliers generate combinatorial blocks with long chains of cascaded carry addition. As such, energy efficiency has remained a primary design challenge for these applications, when powered …
Published in Journal of VLSI Design Tools and Technology Read article
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Inhibitory Potentials of Datura Metel to Prevent Mild Corrosion
Abstract: The resistance of mild steel to corrosion was evaluated by immersing it in well water and determining the weight it lost after being allowed to return to room temperature after the submersion. The effectiveness of mild steel's ability to withstand corrosion was evaluated using this approach. A reduction in total body mass has an influence that is connected to and helps play a role in the prevention of rusting from …
Published in Journal of Polymer & Composites Read article
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Design and Simulation of Low Power Allow Area High Speed Carry Save Adder using CMOS 16 nm Technology.
Abstract: In this article, we propose a novel 1-bit hybrid full adder circuit that is implemented using eighteen transistors. Simulations are done using the Mentor Graphics Tool 16nm technologies. The performances are evaluated based on their speed, average power consumption, and power-delay product. The essential components of arithmetic units including compressors, comparators, parity checkers, etc. are full adders. Thus, raising the performance of the entire adder will raise the system's performance. …
Published in International Journal of VLSI Circuit Design & Technology · Vol. 1, Issue 2, 2023 · pp. 17–28 Read article